Re: Process to combinational circuits?

Discussion in 'VHDL' started by Jim Lewis, Sep 4, 2013.

  1. Jim Lewis

    Jim Lewis Guest

    > Everything that can be done with the process can be done without the
    > process when it comes to combinational, is not it? So what is the
    > justification?

    Yes. For small logic, I use concurrent assignments. For larger more complex code, I use a process.

    Furthermore, the following is a flip-flop. We just need to make sure to file bug reports against synthesis vendors who do not support it:
    AReg <= A when rising_edge(Clk) ;

    There are lots of coding preferences out there. Some say use only a singleclocked process per architecture. My preference is piecewise using smaller pieces of code. However, the only thing that really matters is readable code that gives us insight into the hardware being created.
    Jim Lewis, Sep 4, 2013
    #1
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  2. Jim Lewis

    HT-Lab Guest

    On 04/09/2013 20:08, Jim Lewis wrote:
    >> Everything that can be done with the process can be done without the
    >> process when it comes to combinational, is not it? So what is the
    >> justification?

    > Yes. For small logic, I use concurrent assignments. For larger more complex code, I use a process.
    >
    > Furthermore, the following is a flip-flop. We just need to make sure to file bug reports against synthesis vendors who do not support it:
    > AReg <= A when rising_edge(Clk) ;


    Just checked Mentor's Precision, seems to work fine,

    Hans
    www.ht-lab.com


    >
    > There are lots of coding preferences out there. Some say use only a single clocked process per architecture. My preference is piecewise using smaller pieces of code. However, the only thing that really matters is readable code that gives us insight into the hardware being created.
    >
    HT-Lab, Sep 4, 2013
    #2
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  3. Jim Lewis

    HT-Lab Guest

    On 04/09/2013 21:08, HT-Lab wrote:
    > On 04/09/2013 20:08, Jim Lewis wrote:
    >>> Everything that can be done with the process can be done without the
    >>> process when it comes to combinational, is not it? So what is the
    >>> justification?

    >> Yes. For small logic, I use concurrent assignments. For larger more
    >> complex code, I use a process.
    >>
    >> Furthermore, the following is a flip-flop. We just need to make sure
    >> to file bug reports against synthesis vendors who do not support it:
    >> AReg <= A when rising_edge(Clk) ;

    >
    > Just checked Mentor's Precision, seems to work fine,
    >
    > Hans
    > www.ht-lab.com


    I just checked ISE14.4 which is happy as well, I like this constructs as
    it is short and sweet ;-)

    Thanks,

    Hans
    www.ht-lab.com

    >
    >
    >>
    >> There are lots of coding preferences out there. Some say use only a
    >> single clocked process per architecture. My preference is piecewise
    >> using smaller pieces of code. However, the only thing that really
    >> matters is readable code that gives us insight into the hardware being
    >> created.
    >>

    >
    HT-Lab, Sep 4, 2013
    #3
  4. Jim Lewis

    Andy Guest

    Here are my thoughts on concurrent vs sequential descriptions...

    Humans are sequential thinkers. We understand sequential instructions best.Imagine trying to bake a cake, following a recipe written in concurrent statements that are written in an arbitrary order.

    Furthermore, the synthesis tool is perfectly capable of inferring concurrency from a sequential description where applicable.

    That being said, complexity often dictates breaking down the description ofa complex behavior into multiple concurrent islands of sequential behavior.. This is sometimes useful to clearly indicate independence of behavior (nomatter what that process over there is doing, this process here is doing this...)

    So, here are some loose rules I try to follow:

    Avoid concurrent assignments that depend on each other, or if necessary, state the assignments in order of their dependency (in to out, top to bottom)..

    If two or more signals are controlled by the same set of inputs, use a process to make that joint relationship (e.g. the same case statement) more clear. Concurrent assignments can only affect one signal unless you use aggregate data types and functions or a concurrent procedure call, which, if you are not going to reuse it, is a waste of time and code bulk.

    Anytime combinatorial logic is described in the same architecture as the register it drives, it should be described in the process that assigns the register. Since my preference is to have all outputs from an entity registered, I do not often have combinatorial logic that does not drive a register in the same architecture.

    Cominatorial logic in a clocked process can be described as:

    1) an expression which is assigned to the register,
    2) as a variable written before being assigned to the register,
    3) as a function in an expression being assinged to the register
    4) as a procedure with an output variable

    #3 & #4 are useful when the same combinatorial function feeds register signals or variables in separate clocked processes (since the subprogram can bere-used.)

    If you are relying on code coverage to help define your verification scope/effort, beware that combinatorial processes and concurrent assignments often execute more than once before their value is actually used on the next clock cycle. This can cause lots of false-positive code coverage hits.

    Andy
    Andy, Sep 6, 2013
    #4
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