Re: Q: regarding I2C protocols

Discussion in 'VHDL' started by Wolfgang Denk, Jun 23, 2003.

  1. (y_p_w) writes:

    >So the question I have for those who have really done this is -
    >in the real world, could a master (or series of masters) issue
    >a STOP command followed by a START command - all on the same
    >SCL high period. The latest I2C spec doesn't explain whether
    >or not this could happen.


    Anything can happen. Please consider combinations of fast CPUs and
    sudden power-loss or reset in _all_ phases of the protocol. Remember
    for example the "I2C Edge Conditions" problem.


    Wolfgang Denk

    --
    Software Engineering: Embedded and Realtime Systems, Embedded Linux
    Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Web: www.denx.de
    I have often regretted my speech, never my silence.
     
    Wolfgang Denk, Jun 23, 2003
    #1
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