Re: Quartus warning in NUMERIC_STD.vhd

Discussion in 'VHDL' started by Mike Treseler, Jul 11, 2003.

  1. Alan Fitch wrote:

    >
    > I personally don't think it should be a warning, as it's quite legal
    > to declare null vectors


    I agree.

    A bad assignment to a null vector will cause other errors.
    A null vector declaration alone is innocuous.

    If one bit is 0 to 0 then
    no bits must be 0 to -1

    Let's see:
    -------------------

    entity null_string is
    end null_string;

    architecture sim of null_string
    is
    constant null_vec : std_logic_vector := "";
    constant one_vec : std_logic_vector := "0";
    constant two_vec : std_logic_vector := "00";

    begin

    what : process is
    begin
    report "null_vec is "& integer'image(null_vec'left)
    & " to "& integer'image(null_vec'right);
    report " one_vec is "& integer'image( one_vec'left)
    & " to "& integer'image( one_vec'right);
    report " two_vec is "& integer'image( two_vec'left)
    & " to "& integer'image( two_vec'right);
    wait;
    end process what;

    end sim;

    --VSIM 1> run
    --# ** Note: null_vec is 0 to -1
    --# ** Note: one_vec is 0 to 0
    --# ** Note: two_vec is 0 to 1

    ------------------------

    I suppose that null vectors are rare as signals
    but null vector constants and variables are necessary to make
    clean vector functions.


    --Mike Treseler
    Mike Treseler, Jul 11, 2003
    #1
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  2. Hi, Mike,

    Could please enlighten me on your usage

    integer'image(null_vec'left)

    What's it doing? Is image the function that Ben Cohen provides on his CD
    with his books?

    What is integer' doing? type casting?

    Have I been asleep, or why don't I know about this from all of my reading.

    Please advise, and thank you.

    Clyde

    Mike Treseler wrote:

    > Alan Fitch wrote:
    >
    > >
    > > I personally don't think it should be a warning, as it's quite legal
    > > to declare null vectors

    >
    > I agree.
    >
    > A bad assignment to a null vector will cause other errors.
    > A null vector declaration alone is innocuous.
    >
    > If one bit is 0 to 0 then
    > no bits must be 0 to -1
    >
    > Let's see:
    > -------------------
    >
    > entity null_string is
    > end null_string;
    >
    > architecture sim of null_string
    > is
    > constant null_vec : std_logic_vector := "";
    > constant one_vec : std_logic_vector := "0";
    > constant two_vec : std_logic_vector := "00";
    >
    > begin
    >
    > what : process is
    > begin
    > report "null_vec is "& integer'image(null_vec'left)
    > & " to "& integer'image(null_vec'right);
    > report " one_vec is "& integer'image( one_vec'left)
    > & " to "& integer'image( one_vec'right);
    > report " two_vec is "& integer'image( two_vec'left)
    > & " to "& integer'image( two_vec'right);
    > wait;
    > end process what;
    >
    > end sim;
    >
    > --VSIM 1> run
    > --# ** Note: null_vec is 0 to -1
    > --# ** Note: one_vec is 0 to 0
    > --# ** Note: two_vec is 0 to 1
    >
    > ------------------------
    >
    > I suppose that null vectors are rare as signals
    > but null vector constants and variables are necessary to make
    > clean vector functions.
    >
    > --Mike Treseler
    Clyde R. Shappee, Jul 13, 2003
    #2
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  3. Thanks...

    I guess there are features in VHDL 93 that I have not been aware of. I'll have
    to read up and give them a try.

    CRS

    Mike Treseler wrote:

    > Clyde R. Shappee wrote:
    > > Hi, Mike,
    > >
    > > Could please enlighten me on your usage
    > >
    > > integer'image(null_vec'left)

    >
    > It an integer, the left index of the vector.
    >
    > > What's it doing? Is image the function that Ben Cohen provides on his CD
    > > with his books?

    >
    > No. Standard VHDL. Supported by all the sim and synth tools I have tried.
    >
    > > What is integer' doing? type casting?

    >
    > No. It's a built in VHDL "attribute" , a kind of function.
    >
    > > Have I been asleep, or why don't I know about this from all of my reading.

    >
    > A lot of the cool parts of VHDL-93 were neglected, because
    > they didn't work with every version of every tool.
    > They now work with most versions of most tools, so
    > feel free to use them.
    >
    > -- Mike Treseler
    Clyde R. Shappee, Jul 13, 2003
    #3
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