Re: Question about 2 bit counter example.

Discussion in 'VHDL' started by Skybuck Flying, Aug 2, 2005.

  1. Hmm the code below figure 1-2 of the vhdl cookbook seems to be an
    incrementing counter.

    count:=(count + 1) mod 4
    Q1 := count_value mod 2
    Q2 := count_value / 2

    count value: 0,1,2,3,0,1,2,3
    Q1 : 0,1,0,1,0,1,0,1
    Q2 : 0,0,1,1,0,0,1,1

    While my output shows a decrementing counter.

    Could it be that the cookbook has a wrong picture ?

    Or is there still a flaw somewhere in my reasoning ? ;)

    http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

    Bye,
    Skybuck

    "Skybuck Flying" <> wrote in message news:...
    >
    > "Skybuck Flying" <> wrote in message news:...
    > > Ok,
    > >
    > > Now I understand how these electronics work...
    > >
    > > But I do find it very weird indeed ;)
    > >
    > > First of all the t flip flop only changes state on a fall from 1 to 0

    > (some
    > > flip flops might work opposite but ok)
    > >
    > > Second of all, apperently the "outputs" of the construction/entity has

    to
    > be
    > > read at the same rate as the clock rate.
    > >
    > > Otherwise it doesn't make much sense.
    > >
    > > The first mistake I made was assuming that every 1 bit during the clock

    > rate
    > > would convert the flip flop.
    > >
    > > But this is not the case... the flip flop only changes when the 1 change
    > > from 1 to zero or vice versa...
    > >
    > > So my first assumption that it worked like this was wrong:
    > >
    > > 11001100110011001100
    > >
    > > Suppose a flip flop was connected to this bit stream.
    > >
    > > I thought that each 1 would convert the next flip flop like this:
    > > 10001000100010001000
    > >
    > > Which is wrong ;)
    > >
    > > The flip flop only changes when the input changes from 1 to zero.
    > >
    > > So given the input stream:
    > > 11001100110011001100
    > >
    > > The flip flop output stream would be:
    > > ( assuming it changes on a fall from 1 to zero)
    > > 00111100001111000011
    > >
    > > Etc... truely halving the signal etc.
    > >
    > > Now the last tricky part is in reading the outputs...
    > >
    > > Let's draw it one more time:
    > >
    > > Clock rate: 01010101010101010101
    > > Q1 : 00110011001100110011
    > > Inverter : 11001100110011001100
    > > Q2 : 00001111000011110000

    >
    > Oops I see I messed up here :)
    >
    > Had to take the inverter for Q2 ;)
    >
    > Clock rate: 01010101010101010101
    > Q1 : 00110011001100110011
    > Inverter : 11001100110011001100
    > Q2 : 00111100001111000011
    >
    > So filtering out Q1 and Q2:
    >
    > Q1 : 00110011001100110011
    > Q2 : 00111100001111000011
    >
    > Clock rate: 01#01#01#01#01#01#01#01#01#01
    > Q1 : 00#11#00#11#00#11#00#11#00#11
    > Q2 : 00#11#11#00#00#11#11#00#00#11
    >
    > Reading Q1 and Q2 during the clock tick gives the following stable result:
    >
    > Q1 : 0#1#0#1#0#1#0#1#0#1
    > Q2 : 0#1#1#0#0#1#1#0#0#1
    >
    > Now putting this next to each other:
    >
    > Q1, Q2
    > 00
    > 11
    > 01
    > 10
    > 00
    > 11
    > 01
    > 10
    > 00
    > 11
    > 01
    >
    > Yeah maybe we still need to switch em around ;)
    >
    > 00
    > 11
    > 10
    > 01
    > 00
    > 11
    > 10
    > 01
    > 00
    > 11
    > 10
    >
    > Ok this looks a bit better ;)
    >
    > Apprently a countdown counter ?
    >
    > Or did I mess up again somewhere ? ;)
    >
    > Tricky, tricky,tricky,tricky :)
    >
    > Bye,
    > Skybuck.
    >
    >
    Skybuck Flying, Aug 2, 2005
    #1
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