Re: race conditions in huge project

Discussion in 'VHDL' started by rickman, Jul 31, 2008.

  1. rickman

    rickman Guest

    On Jul 31, 11:52 am, Moritz Schmid <> wrote:
    > Hi,
    >
    > I was recently assigned a huge unfinished vhdl project. Now that I have
    > had a first glance at my predecessor's code, I suspect there to be
    > quite a few race conditions.
    >
    > Does any one have experience with a good and solid method to identify these?
    >
    > My idea would be to insert flags, whether a value was already set in a
    > cycle, and to check for these (maybe with something like an assertion),
    > before using the value to determine new values.
    >
    > Any help would be really appreciated!


    I can't say I am familiar with problems from race conditions other
    than in async logic. If you have async logic in a cycle (a loop) then
    you have potential latches. I suspect I am not really grasping what
    you are describing.

    When you say "cycle" what are you referring to exactly? Is this a
    synchronous design? Is there async feedback?

    The more important design technique for properly implementing a large
    design is partitioning it into smaller designs, each with a clear and
    well defined interface to the rest of the design. It is good to adopt
    a standard way of interfacing these smaller blocks so that you don't
    have to keep track of a lot of complicated details at each
    interface.

    Does any of that help? Can you give more info on your problem?

    Rick
    rickman, Jul 31, 2008
    #1
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