Re: race conditions in huge project

Discussion in 'VHDL' started by jens, Jul 31, 2008.

  1. jens

    jens Guest

    Here's what I would start with:

    1. Is every flip-flop using the same clock? If so, that's good, skip
    ahead to step #4.

    2. Every flip-flop isn't using the same clock: can the design be
    changed to make them all use the same clock? Are any clocks derived
    from a base clock? If so, use only the base clock and create a clock
    enable to replace the derived clocks. If there's only one clock left,
    that's good, skip ahead to step #4.

    3. The design absolutely needs multiple clocks or it would be more
    effort than it's worth to use only one clock: find all signals that
    cross clock domains and fix them if necessary. A signal that's not
    related to other signals can use a simple synchronizer (two flip-flops
    clocked by the destination clock), but multiple related signals (like
    a bus or state machine output, even if it's just two signals) need
    something else like a FIFO or handshaking. If you get that far (FIFO
    or handshaking required), it may be a good time to go back to step #2.

    4. Verify that all IC inputs that go to flip-flops (other than the
    clock, of course) are properly synchronized (see step #3).

    That should take care of asynchronous timing issues, of course there's
    still the simulation/getting it to work phase, not adding any timing
    issues, performing static timing analysis, etc.
    jens, Jul 31, 2008
    #1
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