# Re: random numbers

Discussion in 'VHDL' started by bknpk@hotmail.com, Aug 13, 2013.

1. ### Guest

×‘×ª××¨×™×š ×™×•× ×©× ×™,16 ×‘×¡×¤×˜×ž×‘×¨ 2002 17:55:02 UTC+2, ×ž××ª itsme:
> Hi,
> I like to write a techbench which
> uses random numbers for input data
> to test my hardware.
> Does VHDL has a built in random number generator?
> Is there any library?
> thanks,
> peter

"...
--random numbers generation
signal rand_ttl_delta : std_logic_vector(3 downto 0) := "1000";
signal rand_ttl_deltai : integer := 8;
....
rand_ttl_delta <= f_my_rand (4, rand_ttl_delta);
-- 3 2 1
-- 109876543210987654321098765
if(o_tot_cnt(31 downto 5) = "000000000000000000000000000") then
--small changes during average calculation (learning state)
gen_rand := "00" & rand_ttl_delta(1 downto 0);
else
gen_rand := rand_ttl_delta;
end if;
tmp_ptr.data := tmp_ptr.data + gen_rand;
--
write(my_line, string'("gen_rand "));
hwrite(my_line, tmp_ptr.data);
write(my_line, string'(" "));
--write(my_line, gen_ipv4);
hwrite(my_line, o_tot_cnt);
write(my_line, string'(" "));
write(my_line, now);
writeline(output, my_line);
...."
"...
--random number
function f_my_rand(width : integer; temp_2 : std_logic_vector)
return std_logic_vector is

constant temp_c : std_logic_vector(width-2 downto 0):=
temp_2(width-2 downto 0);
variable rand_temp : std_logic_vector(width-1 downto 0):=
'1' & temp_c;
variable temp : std_logic := '0';
variable random_num : std_logic_vector(width-1 downto 0);
variable my_line : line;
begin
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
random_num := rand_temp;

--if(DEBUG = '1') then
--write(my_line, string'("f_my_rand "));
--hwrite(my_line, random_num);
--writeline(output, my_line);
--end if;
return random_num;
end f_my_rand;
...."

http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_func_rand.html

This was done as part of IP filter VHDL bench and design:
"...
how I randomize the TTL field values. In this project I have already discussed the issue of generating random numbers. While previous case was merely delay between packets, this one is a little bit complex. When the DUT is inlearning state (see FSM description), small changes in the TTL are required. Later an attack scenario is presented to the DUT, by vhdl bench.
...."

, Aug 13, 2013