Re: re: "Writing Makefiles for VHDL models" by Janick Bergeron

Discussion in 'VHDL' started by, Jul 19, 2011.

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    ModelSim and Questa have the vmake command to build a makefile from a compiled library:

    The vmake utility allows you to use a UNIX or Windows MAKE program to maintain individual libraries. You run vmake on a compiled design library. This utility operates on multiple source files per design unit; it supports Verilog include files as well as Verilog and VHDL PSL vunit files.
    , Jul 19, 2011
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