Re: Really Rusty in VHDL...

Discussion in 'VHDL' started by Tricky, Mar 30, 2012.

  1. Tricky

    Tricky Guest


    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.numeric_std.ALL;
    > use IEEE.std_logic_arith.ALL;


    Std_logic_arith and numeric_std packages clash and will cause you problems if you try and use unsigned or signed types. std_logic_arith is non-standard VHDL and should not be used. Numeric_std is the real standard.

    The story is origionally VHDL had no way to handle signed/unsigned arithmatic. Synpopsys wrote std_logic_unsigned/signed and std_logic_arith, which became a defacto standard across the industry. The VHDL working group then wrote numeric_std and released it as part of the IEEE VHDL standard in 1993. Unfortunatly it took a while for vendors to latch on to the real standard, as well as many many engineers and text book writers.
    Tricky, Mar 30, 2012
    #1
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  2. Tricky

    MBodnar Guest

    On Mar 30, 4:21 am, Tricky <> wrote:
    > > library IEEE;
    > > use IEEE.STD_LOGIC_1164.ALL;
    > > use IEEE.numeric_std.ALL;
    > > use IEEE.std_logic_arith.ALL;

    >
    > Std_logic_arith and numeric_std packages clash and will cause you problems if you try and use unsigned or signed types. std_logic_arith is non-standard VHDL and should not be used. Numeric_std is the real standard.
    >
    > The story is origionally VHDL had no way to handle signed/unsigned arithmatic. Synpopsys wrote std_logic_unsigned/signed and std_logic_arith, which became a defacto standard across the industry. The VHDL working group then wrote numeric_std and released it as part of the IEEE VHDL standard in 1993.. Unfortunatly it took a while for vendors to latch on to the real standard, as well as many many engineers and text book writers.


    My biggest advice is to the OP is to always remember to think in terms
    of circuits and not in terms of programming language (with the obvious
    and necessary exceptions: "events" and "sensitivity lists" and "when
    you become experienced enough that there's no difference" etc.).
    Circuit behavior is inherently parallel ... electrons just flow (or
    don't flow), man.

    I don't know what the target hardware is, so I won't make any
    assumptions about your true intention for this code. Envision your
    code as gates; while languages like VHDL are supposed to abstract this
    somewhat, there's always reality, which is in our case is usually
    something physical. (This is course in contrast to an arbitrary
    sequence of finite/fixed operations.)
    MBodnar, Mar 30, 2012
    #2
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