Re: regarding I2C protocols

Discussion in 'VHDL' started by carel harmsen, Jun 23, 2003.

  1. "Tauno Voipio" <_REMOVE.invalid> wrote in
    message news:5LHJa.361$...
    >
    > "rickman" <> wrote in message
    > news:...
    > > Tauno Voipio wrote:
    > > >
    > > > "y_p_w" <> wrote in message
    > > > news:...
    > > > > Hi-
    > > > >
    > > > > I'm currently in the process of creating a synthesizable Verilog
    > > > > F/S I2C slave, but have little experience with I2C in the real
    > > > > world.
    > > > >
    > > > > I'm reading the specs, and I feel I'm getting a pretty good
    > > > > understanding. If I'm getting this right, the SDA line will only
    > > > > change when the SCL line is low - except when the master is
    > > > > indicating a START or STOP command.
    > > > >
    > > > > So the question I have for those who have really done this is -
    > > > > in the real world, could a master (or series of masters) issue
    > > > > a STOP command followed by a START command - all on the same
    > > > > SCL high period. The latest I2C spec doesn't explain whether
    > > > > or not this could happen.
    > > > >
    > > > > This is key to me, since I'm trying to create an I2C slave that
    > > > > runs solely off the SDA and SCL signals. Whether or not I have
    > > > > to deal with START and STOP on the same SCL high period will
    > > > > impact the design choice I make.
    > > > >
    > > >
    > > > AFAIK, that's normal when the bus is idle in the meantime.
    > > >
    > > > The idle bus has all drivers loose and both lines up. When the master

    > ends a
    > > > transmission, the last thing is the STOP condition: SCL up, then SDA

    up.
    > > > When the next transmission starts, the first thing is the START

    > condition:
    > > > SCL still up, SDA down.

    > >
    > > I think he means the other way around, a START followed by a STOP with
    > > no clock transitions inbetween. In essence, this would be an "empty"
    > > frame.
    > >
    > > I have not worked with I2C before, so I don't know the answer. But I am
    > > interested since I will be making one as well.
    > >
    > > I have not checked opencores.org, but it seems likely that they would
    > > have a core for this. It might be a bit larger than you would want to
    > > use however.
    > >

    >
    > An empty frame is expressely forbidden in the specs. However, the logic

    must
    > still not hang up if such a condition should happen.
    >
    > Tauno Voipio
    > tauno voipio @ iki fi
    >
    >

    Hi, I have done this with a Lattice 1016 (64 registers)
    The start condition, SCL high and SDA falling is to put the device in
    lets call it "address compare mode", if the address (Bit 1-7) matches the
    device goes
    into "read or write mode" depending on bit0 , otherwise the "I'm not
    interested mode",
    i.e. the "not address compare mode" and "not read read or write mode"

    This is determined at the rising edge of the 9th SCL pulse. So the start
    condition is
    a mode reset command. Note that controllers like the PCF8584 have slow
    rising
    and falling signals. Your FPGA will be ways too fast for this, so you will
    have
    to register the signals to determine the transitions.

    Example: clock speed 1Mhz (actual speed)
    SCL2 = SCL1 = SCL
    Not_SCL2 And SCL1 = transitionevent

    Tip: in read/write mode where the 9th SCL pulse is used for ACK generation
    you can also use the rising edge to generate a read or write pulse to
    communicate
    with a device. With this you can have a continuous 8-bit data stream into or
    from
    the device. Ideal for a graphical LCD-display (and whenever there is a
    connection
    with a high frequency and a low frequency device)

    Carel Harmsen
    carel harmsen, Jun 23, 2003
    #1
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