Re: regarding I2C protocols

Discussion in 'VHDL' started by y_p_w, Jun 24, 2003.

  1. y_p_w

    y_p_w Guest

    "Tauno Voipio" <_REMOVE.invalid> wrote in message news:<5LHJa.361$>...
    > "rickman" <> wrote in message
    > news:...
    > > Tauno Voipio wrote:
    > > >
    > > > "y_p_w" <> wrote in message
    > > > news:...
    > > > > Hi-
    > > > >
    > > > > I'm currently in the process of creating a synthesizable Verilog
    > > > > F/S I2C slave, but have little experience with I2C in the real
    > > > > world.
    > > > >
    > > > > I'm reading the specs, and I feel I'm getting a pretty good
    > > > > understanding. If I'm getting this right, the SDA line will only
    > > > > change when the SCL line is low - except when the master is
    > > > > indicating a START or STOP command.
    > > > >
    > > > > So the question I have for those who have really done this is -
    > > > > in the real world, could a master (or series of masters) issue
    > > > > a STOP command followed by a START command - all on the same
    > > > > SCL high period. The latest I2C spec doesn't explain whether
    > > > > or not this could happen.
    > > > >
    > > > > This is key to me, since I'm trying to create an I2C slave that
    > > > > runs solely off the SDA and SCL signals. Whether or not I have
    > > > > to deal with START and STOP on the same SCL high period will
    > > > > impact the design choice I make.
    > > > >
    > > >
    > > > AFAIK, that's normal when the bus is idle in the meantime.
    > > >
    > > > The idle bus has all drivers loose and both lines up. When the master

    > ends a
    > > > transmission, the last thing is the STOP condition: SCL up, then SDA up.
    > > > When the next transmission starts, the first thing is the START

    > condition:
    > > > SCL still up, SDA down.

    > >
    > > I think he means the other way around, a START followed by a STOP with
    > > no clock transitions inbetween. In essence, this would be an "empty"
    > > frame.
    > >
    > > I have not worked with I2C before, so I don't know the answer. But I am
    > > interested since I will be making one as well.
    > >
    > > I have not checked opencores.org, but it seems likely that they would
    > > have a core for this. It might be a bit larger than you would want to
    > > use however.
    > >

    >
    > An empty frame is expressely forbidden in the specs. However, the logic must
    > still not hang up if such a condition should happen.
    >
    > Tauno Voipio
    > tauno voipio @ iki fi



    Thanks for the answer. I actually re-read the spec, and noticed
    that a STOP following a START in the same SCL high period is illegal.
    I'm going to ignore an illegally applied STOP (i.e. illegal STOP
    ignored). I was also worried about the possibility of repeated STOP/
    START/STOP/START sequences.

    However - as a follow-up question, would it be possible to see SCL
    toggle after a STOP before the next START command "in the real world"?
    None of the timing diagrams in the spec seem to address this
    possibility; all diagrams show SDA and SCL staying high for the
    foreseeable future. I'd guess that the thing to do is simply put
    put the I2C slave in a wait state until a START condition is seen. I
    wouldn't see any reason to toggle SCL between a STOP and the next
    START, but I haven't seen any real-world designs.

    Again - many thanks for the replies.
     
    y_p_w, Jun 24, 2003
    #1
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  2. y_p_w

    Gerard Guest

    >
    > Thanks for the answer. I actually re-read the spec, and noticed
    > that a STOP following a START in the same SCL high period is illegal.
    > I'm going to ignore an illegally applied STOP (i.e. illegal STOP
    > ignored). I was also worried about the possibility of repeated STOP/
    > START/STOP/START sequences.
    >
    > However - as a follow-up question, would it be possible to see SCL
    > toggle after a STOP before the next START command "in the real world"?
    > None of the timing diagrams in the spec seem to address this
    > possibility; all diagrams show SDA and SCL staying high for the
    > foreseeable future. I'd guess that the thing to do is simply put
    > put the I2C slave in a wait state until a START condition is seen. I
    > wouldn't see any reason to toggle SCL between a STOP and the next
    > START, but I haven't seen any real-world designs.
    >
    > Again - many thanks for the replies.


    Hi



    Well that's what really matters (IHO), "the real world". And in the real
    world everything is possible. You can have a lousy implemented
    micro-controller software I2C or even if you are debugging the hardware you
    can accidentally toggle a line. I know applications where they misuse the
    spec and by driving the SCL low between STOP and START for a certain time,
    they signal other devices for example busmaster takeover. Everything is
    possible.



    If you are designing this for a real application you have to deal with the
    real world and you must handle all the situations you can think off. It's
    very clumsy if your hardware is 'hanging'. Master controllers are build
    by spec's and slaves by sense.



    Gerard



    www.stacktools.com
     
    Gerard, Jun 24, 2003
    #2
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