Re: Repetitive code (Newbie)

Discussion in 'VHDL' started by Jerry, Aug 6, 2003.

  1. Jerry

    Jerry Guest

    "smu" <> wrote in message news:<3f2fd735$0$16171$>...
    > I try to find a elegant way to code a component in order to employ it with
    > different value of a constant.
    > ....

    You will have to use generics and for..generate.
    Since you are using attributes to specify single rom16x1 component
    contents, the solution is not the nicest one:
    --------start---------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity c_nibble is
    generic ( busmax : integer := 3;
    inits : string := "926C4B5A99CC552A" );
    port ( input : in std_logic_vector(3 downto 0);
    output : out std_logic_vector(busmax downto 0));
    end c_nibble;

    architecture c_nibble_a of c_nibble is
    component rom16x1
    port( a3, a2, a1, a0 : in std_logic;
    o : out std_logic);
    end component;
    attribute init : string;
    begin
    rom: for i in busmax downto 0 generate
    attribute init of blk : label is
    inits((busmax-i)*4+1 to (busmax-i)*4+4 );
    begin
    blk: rom16x1 port map ( a3 => input(3), a2 => input(2), a1 => input(1),
    a0 => input(0), o => output(i));
    end generate rom;
    end c_nibble_a;
    -----------stop------------

    VHDL 93 compliant compiler is required to handle this code.

    Good luck!

    Jerry
     
    Jerry, Aug 6, 2003
    #1
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  2. Jerry

    smu Guest

    Which would be the nicest solution to initialize the ROM blocks ?

    smu

    "Jerry" <> a écrit dans le message de news:
    ...
    > "smu" <> wrote in message

    news:<3f2fd735$0$16171$>...
    > > I try to find a elegant way to code a component in order to employ it

    with
    > > different value of a constant.
    > > ....

    > You will have to use generics and for..generate.
    > Since you are using attributes to specify single rom16x1 component
    > contents, the solution is not the nicest one:
    > --------start---------
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    >
    > entity c_nibble is
    > generic ( busmax : integer := 3;
    > inits : string := "926C4B5A99CC552A" );
    > port ( input : in std_logic_vector(3 downto 0);
    > output : out std_logic_vector(busmax downto 0));
    > end c_nibble;
    >
    > architecture c_nibble_a of c_nibble is
    > component rom16x1
    > port( a3, a2, a1, a0 : in std_logic;
    > o : out std_logic);
    > end component;
    > attribute init : string;
    > begin
    > rom: for i in busmax downto 0 generate
    > attribute init of blk : label is
    > inits((busmax-i)*4+1 to (busmax-i)*4+4 );
    > begin
    > blk: rom16x1 port map ( a3 => input(3), a2 => input(2), a1 =>

    input(1),
    > a0 => input(0), o => output(i));
    > end generate rom;
    > end c_nibble_a;
    > -----------stop------------
    >
    > VHDL 93 compliant compiler is required to handle this code.
    >
    > Good luck!
    >
    > Jerry
     
    smu, Aug 7, 2003
    #2
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  3. Mike Treseler, Aug 7, 2003
    #3
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