Re: Shift Register Operation

Discussion in 'VHDL' started by Nicolas Matringe, Nov 25, 2004.

  1. Weddick a écrit:
    > Just starting with VHDL and was trying to make a serial shift register to
    > shift in 8 bits. I have attached my code and test bench. The problem I
    > have is that it seems the data takes an extra clock before it becomes
    > availabe at the output. Any help would be appreciated.


    Hi
    That's what you wrote in your VHDL :eek:)
    Data bits are shifted in you data register on every clock edge, and this
    data register is then copied in your dword output register. That makes 2
    clock cycles between din and dword.
    Just put the 'dword <= data;' assignment outside of the process, or use
    a variable instead of a signal for data.
    You should use a reset signal for your registers.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Nov 25, 2004
    #1
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