Re: Signal/Variable Initial Vaues and Evils of Asynchronous Reset

Discussion in 'VHDL' started by Tricky, May 30, 2010.

  1. Tricky

    Tricky Guest

    On May 29, 9:56 pm, Wendigo <> wrote:
    > I have a book that says the following regarding initial values for signals
    > and variables...
    > "VARIABLE control: BIT := 0;
    > ...Also, like in the case of a SIGNAL, the initial value in the syntax above
    > is not synthesizable, being only considered in simulations."
    > The documentation from my vendor explicitly states that it supports this
    > (for signals and variables that are registered at least):
    > "When you give a register an initial value in a declaration, XST sets this
    > value on the output of the register at global reset, or at power up. The
    > assigned value is carried in the NGC file as an INIT attribute on the
    > register, and is independent of any local reset."
    > Are there certain vendors that don't support this?  Is it not
    > supported by certain technologies?  (ASICs, perhaps?)  
    > I'm just curious how portable (across tools and technologies) this is.
    > Also...  This isn't necessarily VHDL related but I've read some of the
    > messages in this group about the problems with asynchronous reset and now
    > I have a question.
    > Can the GSR signal (Global Set/Reset, I'm guessing this is a
    > vendor-specific term) be used for synchronous reset?  I don't see anything
    > in the datasheet for my particular device (Xilinx XC9572XL) that says
    > that it can or can't.  My design runs at only 32.768kHz so I'm worried the
    > GSR signal won't still be asserted when a rising clock edge comes along.
    > I couldn't find any app. notes that specifically state that GSR will be
    > asserted for a least one complete clock cycle in order to guarantee a
    > synchronous reset.

    Altera wont infer power up values using default assignments for
    registers, but they are obviously very useful in simulation. It will
    however allow you to set the power-up values of an infered ram either
    via a constant or function call (though they still wont allow you to
    use textio to read a text file like Xilinx do!) Altera will infer
    power up reset values from the asynchronous reset functionality
    though, so it can be useful to to create an async reset even if you
    plan to connect it to '0';
    Tricky, May 30, 2010
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