Re: Signal within block

Discussion in 'VHDL' started by Mike Treseler, Aug 23, 2003.

  1. Isaac wrote:

    > I am using 12 same entitites using Component decleration method.


    Perhaps you mean a top architecture with 12 instances of some entity.

    > I am
    > giving input to 12 entities in such a way that the internal signal's
    > in each entity has different values from each other at any time. Now
    > the top vhdl final in which all the component decleration are defined
    > , I want to use the internal signal's of each block to perform some
    > calculation. The probelm is that in each of the 12 entities signal has
    > the same name (as I am using component decleration method to generate
    > same entity 12 time).


    Each instance has a unique label:

    my_entity_1 : entity work.my_entity
    port map (reset => reset_sig, -- [in]
    clk => clk_sig, -- [in]
    i => i_1_sig, -- [in]
    o => o_1_sig); -- [out]

    my_entity_12 : entity work.my_entity
    port map (reset => reset_sig, -- [in]
    clk => clk_sig, -- [in]
    i => i_12_sig, -- [in]
    o => o_12_sig); -- [out]

    The signal associated with an instance port is whatever
    you define it to be in the port map.
    I think of this as "wiring up" the instances.
    These "wire" signals must be declared between
    the IS and BEGIN of the top architecture.
    It can be a different signal for each instance if you like.

    > Is there is any way to access these Signal in VHDL?


    These signals are accessible anywhere in the top architecture.

    -- Mike Treseler
     
    Mike Treseler, Aug 23, 2003
    #1
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