Re: Signed multiplication revisited

Discussion in 'VHDL' started by Andy, Sep 10, 2008.

  1. Andy

    Andy Guest

    On Sep 10, 1:16 pm, Brian Drummond <>
    wrote:
    > (Incidentally,  using variables instead of signals does exactly the same
    > thing; i.e. works exactly as expected. Writing the multiplications out
    > longhand in the process, instead of using a procedure, works as
    > expected. But if you have an array of multiplications, it gets ugly.)


    That's what loops and arrays of vectors are for... ;^)

    I just wish there was a way to synthesize procedures that span clock
    cycles, rather than having to pass inout args for intermediate outputs/
    registers. OTOH, most of the cases where I would want that, I would
    need a fork/join type capability to avoid a separate process anyway.

    Interesting... especially since XST figures it out correctly with
    variables. FYI, I just checked it with Synplify, and it works
    correctly regardless of the order of signal assignments in the
    procedure.

    Andy
    Andy, Sep 10, 2008
    #1
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  2. Andy wrote:

    > I just wish there was a way to synthesize procedures that span clock
    > cycles, rather than having to pass inout args for intermediate outputs/
    > registers.


    I assume you are ruling out procedures declared
    or overloaded in process scope.

    These synthesize just fine for any register structure declared
    in the same process.

    -- Mike Treseler
    Mike Treseler, Sep 29, 2008
    #2
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