Re: simulation limit

Discussion in 'VHDL' started by JimLewis, Dec 7, 2009.

  1. JimLewis

    JimLewis Guest

    I too use the same simulation run times. Just to clarify
    something that Mike said:

    > By the way, a gate sim is a test of your
    > tools, rules and testbench, not your design.


    One set of rules are coding style rules. If you violate
    coding style rules, your gate design will have issues that
    are not able to be identified in RTL simulations.

    For example,
    Y <= A after 20 ns ;

    If your clock period is 10 ns, this simulates in a similar
    fashion to two flip-flops. However, in synthesis, no
    hardware will be created for after, so your gate simulations
    will differ from your RTL sims.

    Best,
    Jim
    SynthWorks
    JimLewis, Dec 7, 2009
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Neil Zanella

    VHDL Simulation for Linux

    Neil Zanella, Jun 25, 2003, in forum: VHDL
    Replies:
    2
    Views:
    19,663
    =?ISO-8859-1?Q?Uwe_Klo=DF?=
    Aug 4, 2003
  2. Replies:
    1
    Views:
    1,069
    Victor Bazarov
    Jun 28, 2005
  3. jasperng
    Replies:
    0
    Views:
    1,296
    jasperng
    Nov 27, 2008
  4. THurkmans
    Replies:
    2
    Views:
    810
    Tricky
    Aug 27, 2009
  5. JSreeniv

    simulation limit

    JSreeniv, Dec 7, 2009, in forum: VHDL
    Replies:
    3
    Views:
    561
    Thomas Stanka
    Dec 8, 2009
Loading...

Share This Page