Re: Simulation warning in Modelsim

Discussion in 'VHDL' started by Naimesh Thakkar, Sep 16, 2004.

  1. Yes I did but I didnt got any reply so I thought of putting it on
    comp.lang.vhdl anyways thanks for explanining..

    Naimesh
     
    Naimesh Thakkar, Sep 16, 2004
    #1
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