Re: Synchronization of data

Discussion in 'VHDL' started by deep, Apr 15, 2004.

  1. deep

    deep Guest

    i feel that Ist stage DFF shall be sufficient as passing the external clock
    through the DFF would result in bad synchronisation...

    from the figure it seems that PLL is not required and a simple buffer
    would do...

    dk
    deep, Apr 15, 2004
    #1
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