Re: systemC and OSVVM

Discussion in 'VHDL' started by alb, Apr 15, 2014.

  1. alb

    alb Guest

    My apologies, I should have really cross-posted this subthread to
    comp.lang.vhdl as well in the first place. alb <>
    wrote:
    > Hi Hans,
    > In comp.arch.fpga HT-Lab <> wrote:
    > []
    >>> I'm considering the possibility to have my model written in SystemC
    >>> while the testbench written in vhdl, leveraging the benefits of the
    >>> OSVVM library.

    >>
    >> That is unusual, I suspect you are better off using SCV as you might hit
    >> some mix language interface issues (records are not always
    >> straightforward on a SC/VHDL interface, use simple structs on SC only).

    >
    > There are two motivations behind this choice:
    >
    > 1. our system engineer is willing to dig into systemC for architecture
    > exploration in the first place. We can profit of the model in order to
    > build our verification environment *soon* in the project.
    >
    > 2. our fpga guys are not so much willing to spend time in learning
    > systemC, while they could feel more confortable with the OSVVM since
    > they know already the language.
    >
    > The first point is a structural element that we are missing in our
    > design flow. Too often the architecture is based on not so well founded
    > choices and as the systems grow more complex, there's an increasing need
    > to get the architecture right at the very beginning.
    >
    > The second point is to enhance our current verification flow which is
    > too often lagging behind. There's an unreasonable perception that going
    > to the bench soon will reveal problems quicker. If we had a reference
    > model and a verification environment early in the project I believe we
    > can shift our mindset and spend less time in testing/debugging the
    > hardware.
    alb, Apr 15, 2014
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. goose

    systemC and modelsim

    goose, Jun 29, 2006, in forum: VHDL
    Replies:
    1
    Views:
    677
    goose
    Jun 29, 2006
  2. goose

    systemC and modelsim

    goose, Jun 29, 2006, in forum: C Programming
    Replies:
    1
    Views:
    2,880
    goose
    Jun 29, 2006
  3. Jim Lewis
    Replies:
    0
    Views:
    431
    Jim Lewis
    May 1, 2013
  4. Jim Lewis
    Replies:
    0
    Views:
    351
    Jim Lewis
    Jul 8, 2013
  5. alb
    Replies:
    1
    Views:
    229
    Jim Lewis
    Dec 6, 2013
Loading...

Share This Page