Re: testbench techniques

Discussion in 'VHDL' started by FMF, Nov 27, 2005.

  1. FMF

    FMF Guest

    Adam,

    In addition to the other suggestions you got, consider including models
    of the components your FPGA interfaces with as part of your verification
    environment. The Free Model Foundry (http://www.FreeModelFoundry.com)
    offers many models built for just this purpose. And, as the name
    implies, they will not cost a thing.

    Regards,
    Rick


    mindenpilot wrote:
    > All,
    >
    > I'm about to embark on my second large FPGA project.
    > The first one was a success, with very few bugs.
    > However, my testbenches were somewhat of a hack.
    > I simply modeled whatever the UUT was interfacing to, then looked at the
    > timing diagrams.
    >
    > I'd like to design more comprehensive tests, and I'm sure there are proper
    > techniques for this.
    > For example, I didn't even use any text output.
    > I'm sure my old approach will work for this new design, but I'd like to
    > improve.
    >
    > Part of the problem is that FPGAs are new to our company.
    > Mine was the first project to use one.
    > We have no expertise, and I am trying to make sure that our foundation is
    > solid.
    >
    > So, if you have expertise, and would like to share what has worked for you,
    > I would appreciate it.
    > Or, if you have references that you find useful, that would work, too.
    >
    > I know there are books about testbenches out there.
    > But what I'm looking for is a few rules of thumb that are best practices
    > (kind of like the commandments that were posted here).
    >
    > Regards,
    >
    > Adam
    >
    >
    >
    FMF, Nov 27, 2005
    #1
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  2. FMF

    mindenpilot Guest

    Wow, what a great resource.
    Thanks for the input.
    Part of my current design includes an SDRAM controller, and I saw a model
    for it in there.
    That should really help with the testbench.
    Thanks for pointing this out!

    Regards,

    Adam Weiss


    "FMF" <> wrote in message
    news:...
    > Adam,
    >
    > In addition to the other suggestions you got, consider including models of
    > the components your FPGA interfaces with as part of your verification
    > environment. The Free Model Foundry (http://www.FreeModelFoundry.com)
    > offers many models built for just this purpose. And, as the name implies,
    > they will not cost a thing.
    >
    > Regards,
    > Rick
    >
    >
    > mindenpilot wrote:
    >> All,
    >>
    >> I'm about to embark on my second large FPGA project.
    >> The first one was a success, with very few bugs.
    >> However, my testbenches were somewhat of a hack.
    >> I simply modeled whatever the UUT was interfacing to, then looked at the
    >> timing diagrams.
    >>
    >> I'd like to design more comprehensive tests, and I'm sure there are
    >> proper techniques for this.
    >> For example, I didn't even use any text output.
    >> I'm sure my old approach will work for this new design, but I'd like to
    >> improve.
    >>
    >> Part of the problem is that FPGAs are new to our company.
    >> Mine was the first project to use one.
    >> We have no expertise, and I am trying to make sure that our foundation is
    >> solid.
    >>
    >> So, if you have expertise, and would like to share what has worked for
    >> you, I would appreciate it.
    >> Or, if you have references that you find useful, that would work, too.
    >>
    >> I know there are books about testbenches out there.
    >> But what I'm looking for is a few rules of thumb that are best practices
    >> (kind of like the commandments that were posted here).
    >>
    >> Regards,
    >>
    >> Adam
    >>
    >>
    >>

    >
    mindenpilot, Nov 28, 2005
    #2
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