Re: Two processes writing one signal

Discussion in 'VHDL' started by Phil Hays, Jun 30, 2003.

  1. Phil Hays

    Phil Hays Guest

    Jeremy Pyle wrote:
    >
    > Ok, I got a problem. I have two processes inside an architecture writing
    > the same signal. One process runs at startup and initializes the signal
    > while the other one runs after that, it's guaranteed that they never run at
    > the same time. However, when I simulate it the signal, which is local to
    > the architecture, never leaves the U value. If I comment out the write in
    > the second process(not the initialization one), then the signal changes like
    > it's supposed to. I know if two modules both write to one data bus then
    > when one is writing the other must write all Z's, is this also true for
    > signals in an architecture?


    Yes. STD_LOGIC Signals driven between processes are multi-state buses
    driven by multiple drivers.

    If this is a test bench, you might be able to make good use of "H" and
    "L" (weak 1 and 0). I wouldn't count on a synthesiser mapping these
    correctly. And you may need the function TO_X01 to avoid having to
    write:

    If name = '1' or name ='H' then


    --
    Phil Hays
    Phil Hays, Jun 30, 2003
    #1
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  2. Phil Hays

    Jeremy Pyle Guest

    Well, or writing all Z's while the other process is updating will work too
    right?


    "Phil Hays" <> wrote in message
    news:...
    > Jeremy Pyle wrote:
    > >
    > > Ok, I got a problem. I have two processes inside an architecture

    writing
    > > the same signal. One process runs at startup and initializes the signal
    > > while the other one runs after that, it's guaranteed that they never run

    at
    > > the same time. However, when I simulate it the signal, which is local

    to
    > > the architecture, never leaves the U value. If I comment out the write

    in
    > > the second process(not the initialization one), then the signal changes

    like
    > > it's supposed to. I know if two modules both write to one data bus then
    > > when one is writing the other must write all Z's, is this also true for
    > > signals in an architecture?

    >
    > Yes. STD_LOGIC Signals driven between processes are multi-state buses
    > driven by multiple drivers.
    >
    > If this is a test bench, you might be able to make good use of "H" and
    > "L" (weak 1 and 0). I wouldn't count on a synthesiser mapping these
    > correctly. And you may need the function TO_X01 to avoid having to
    > write:
    >
    > If name = '1' or name ='H' then
    >
    >
    > --
    > Phil Hays
    Jeremy Pyle, Jun 30, 2003
    #2
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