Re: Two questions(XiLinx synthesis)

Discussion in 'VHDL' started by Pedro Claro, Aug 1, 2003.

  1. Pedro Claro

    Pedro Claro Guest

    Did you try the solution record in the xilinx website?


    "Christopher Bunk" <> wrote in message news:<SmcWa.54845$>...
    > Ok, I have two questions.
    >
    > 1. When I run the synthesis tools it breaks up the chip usage into like 5
    > different categories(slices, flip flop slices, IOBs, GCLK and LUT). It
    > seems I'm running out of slices. What exactly is a slice and does anyone
    > have any suggestions on how to use less of these?
    >
    > 2. When I synthesize, I get the following warning: WARNING:Xst:1290 -
    > Hierarchical block <I3> is unconnected in block <Mmux__n0008>.It will be
    > removed from the design.
    >
    > Now I realize this is only a warning and it synthesizes fine, but what
    > exactly does this mean and how do I get rid of it?
    >
    > Thanks.
     
    Pedro Claro, Aug 1, 2003
    #1
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  2. Re: compile error c0044: resolution is an undefined resolution function

    I updated my email address..First post does not haev the correct email
    address

    If someone doesn't know why I am getting the compile error, maybe
    soemone could point me to understand what C0044 means? A error
    definition book..that has more information.

    Thank you

    Dennis

    lid wrote:
    > Hello
    >
    > I am getting a compile error on this line in the file fourbitadder.vhd
    >
    > SIGNAL im : faulty_resolution2 sulog_fault_array;
    >
    > C0044: faulty_resolution2 is an undefined resolution function
    >
    > I have no idea why it says that when it is clearly defined in the code
    > only a few lines above it!
    >
    > Anyone know why I am getting this error message?
    >
    > Thank you in advance
    >
    > Dennis
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    >
    > PACKAGE problem_2 IS
    >
    > TYPE fault IS (sa1, sa0, nofault);
    >
    > TYPE std_ulogic_faultable IS RECORD
    > log : std_ulogic;
    > fau : fault;
    > END RECORD;
    >
    >
    > TYPE stdlogic_table IS ARRAY (std_ulogic, std_ulogic) OF std_ulogic;
    > CONSTANT resolution_table : stdlogic_table := (
    > ------------------------------------------------------------
    > --| U X 0 1 Z W L H - | |
    > ------------------------------------------------------------
    > ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
    > ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
    > ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
    > ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
    > ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
    > ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
    > ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |
    >
    >
    > TYPE sulog_fault_array is ARRAY (NATURAL RANGE <>) OF std_ulogic_faultable ;
    > -- TYPE sulog_fault_array is ARRAY (32 DOWNTO 0) OF std_ulogic_faultable ;
    >
    > FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN std_ulogic_faultable ;
    >
    > -- SUBTYPE wired_std_ulogic_faultable IS faulty_resolution std_ulogic_faultable;
    >
    > -- ##### Part D ######
    > CONSTANT and_table : stdlogic_table := (
    > ------------------------------------------------------------
    > --| U X 0 1 Z W L H - | |
    > ------------------------------------------------------------
    > ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
    > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
    > ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
    > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
    > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
    > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
    > ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
    > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
    > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); -- | - |
    >
    >
    > CONSTANT xor_table : stdlogic_table := (
    > ------------------------------------------------------------
    > --| U X 0 1 Z W L H - | |
    > ------------------------------------------------------------
    > ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
    > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
    > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
    > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
    > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
    > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |
    >
    >
    > TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
    >
    > CONSTANT not_table : stdlogic_1d :=
    > ------------------------------------------------------------
    > --| U X 0 1 Z W L H - | |
    > ------------------------------------------------------------
    > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
    >
    >
    > FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
    > FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
    >
    >
    >
    > TYPE fault_vector IS ARRAY (8 DOWNTO 0) OF fault;
    > TYPE fault_array IS ARRAY (3 DOWNTO 0) OF fault_vector;
    >
    > END problem_2;
    >
    > PACKAGE BODY problem_2 IS
    >
    >
    > FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN std_ulogic_faultable IS
    > -- record std_ulogic_faultable = (log, fau)
    > -- log = std_ulogic
    > -- fau = (sa1, sa0, nofault)
    >
    > VARIABLE logic_temp : std_ulogic ;
    > VARIABLE fault_temp : fault := nofault;
    >
    > BEGIN
    >
    > FOR i IN drivers'RANGE LOOP
    >
    > IF drivers(i).fau = sa0 THEN
    > logic_temp := '0';
    > fault_temp := sa0;
    > EXIT;
    > ELSIF drivers(i).fau = sa1 THEN
    > logic_temp := '1';
    > fault_temp := sa1;
    > EXIT;
    > ELSIF drivers(i).fau = nofault THEN
    > logic_temp := resolution_table (logic_temp, drivers(i).log);
    > fault_temp := drivers(i).fau;
    > end IF;
    >
    > END LOOP;
    >
    > RETURN (logic_temp, fault_temp);
    >
    > END faulty_resolution;
    >
    > --####### Part D ######
    >
    > FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
    > variable temp : std_ulogic;
    > BEGIN
    >
    > temp := and_table(l, r);
    >
    > RETURN not_table(temp);
    >
    > END "nand";
    >
    >
    > FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
    > BEGIN
    >
    > RETURN xor_table (l, r);
    >
    > END "xor";
    >
    > END problem_2 ;
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > USE WORK.problem_2.ALL;
    > --
    > --
    > -- ## 4-bit Adder
    > ENTITY fourbitadder IS
    > GENERIC (faults : fault_array := (
    > 0 => (0=> sa1, OTHERS => sa0),
    > -- 0 => (OTHERS => nofault),
    > 1 => (OTHERS => nofault),
    > 2 => (OTHERS => nofault),
    > 3 => (OTHERS => nofault)));
    >
    > PORT (a, b : IN sulog_fault_array(3 DOWNTO 0);
    > cin : IN std_ulogic_faultable;
    > sum : OUT sulog_fault_array(3 DOWNTO 0);
    > cout : OUT std_ulogic_faultable);
    >
    > END fourbitadder;
    > --
    > ARCHITECTURE structural OF fourbitadder IS
    >
    > FUNCTION faulty_resolution2 (drivers : sulog_fault_array ) RETURN std_ulogic_faultable IS
    > -- record std_ulogic_faultable = (log, fau)
    > -- log = std_ulogic
    > -- fau = (sa1, sa0, nofault)
    >
    > VARIABLE logic_temp : std_ulogic ;
    > VARIABLE fault_temp : fault := nofault;
    > VARIABLE temp_comb : std_ulogic_faultable;
    >
    > BEGIN
    >
    > FOR i IN drivers'RANGE LOOP
    >
    > IF drivers(i).fau = sa0 THEN
    > logic_temp := '0';
    > fault_temp := sa0;
    > EXIT;
    > ELSIF drivers(i).fau = sa1 THEN
    > logic_temp := '1';
    > fault_temp := sa1;
    > EXIT;
    > ELSIF drivers(i).fau = nofault THEN
    > logic_temp := resolution_table (logic_temp, drivers(i).log);
    > fault_temp := drivers(i).fau;
    > end IF;
    >
    > END LOOP;
    > temp_comb := (logic_temp, fault_temp);
    >
    > RETURN temp_comb;
    >
    > END faulty_resolution2;
    >
    > --SUBTYPE fault_res IS faulty_resolution std_ulogic_faultable ;
    > --TYPE fault_res_array IS ARRAY (32 DOWNTO 0) OF fault_res;
    >
    > COMPONENT xor2
    > PORT (i1, i2 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    > END COMPONENT;
    > COMPONENT nand2
    > PORT (i1, i2 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    > END COMPONENT;
    > COMPONENT nand3
    > PORT (i1, i2, i3 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    > END COMPONENT;
    >
    >
    >
    > SIGNAL im : faulty_resolution2 sulog_fault_array;
    >
    >
    > BEGIN
    > im(0) <= cin;
    > -- fulladders
    >
    > iti : FOR i IN 0 TO 3 GENERATE
    > -- wires of each fulladder
    >
    > itj : FOR j IN 0 TO 8 GENERATE
    > -- inject fault
    > im(i*8+j).fau <= faults(i)(j);
    > im(i*8+j).log <= '0' WHEN (faults(i)(j) = sa0) ELSE
    > '1' WHEN (faults(i)(j) = sa1) ELSE 'Z';
    > END GENERATE;
    >
    > --fulladder
    > im(i*8+1) <= a(i);
    > im(i*8+2) <= b(i);
    > x1 : xor2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+3));
    > x2 : xor2 PORT MAP (im(i*8), im(i*8+3), im(i*8+7));
    > n1 : nand2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+4));
    > n2 : nand2 PORT MAP (im(i*8), im(i*8+1), im(i*8+5));
    > n3 : nand2 PORT MAP (im(i*8), im(i*8+2), im(i*8+6));
    > n4 : nand3 PORT MAP (im(i*8+4), im(i*8+5), im(i*8+6), im((i+1)*8));
    > sum(i) <= im(i*8+7);
    > END GENERATE;
    >
    > cout <= im(32);
    >
    > END structural;
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > USE WORK.problem_2.ALL;
    >
    > ENTITY nand2 IS
    >
    > PORT (i1, i2 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    >
    > END nand2;
    > --
    > ARCHITECTURE dataflow OF nand2 IS
    >
    > BEGIN
    >
    > PROCESS (i1, i2)
    > BEGIN
    > IF i1.fau = sa0 OR i2.fau = sa0 THEN
    > o1 <= ('1', nofault);
    > ELSIF i1.fau = sa1 THEN
    > o1 <= (('1' nand i2.log), nofault);
    > ELSIF i2.fau = sa1 THEN
    > o1 <= ((i1.log nand '1'), nofault);
    > ELSE
    > o1 <= (( i1.log nand i2.log), nofault);
    > END IF;
    > END PROCESS;
    >
    > END dataflow;
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > USE WORK.problem_2.ALL;
    >
    > ENTITY nand3 IS
    >
    > PORT (i1, i2, i3 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    >
    > END nand3;
    > --
    > ARCHITECTURE dataflow OF nand3 IS
    >
    > BEGIN
    >
    > PROCESS (i1, i2, i3)
    > BEGIN
    > IF i1.fau = sa0 OR i2.fau = sa0 OR i3.fau = sa0 THEN
    > o1 <= ('1', nofault);
    > ELSIF i1.fau = sa1 THEN
    > o1 <= ( (and_table('1',i2.log) nand i3.log), nofault);
    > ELSIF i2.fau = sa1 THEN
    > o1 <= ( (and_table(i1.log, '1') nand i3.log), nofault);
    > ELSIF i3.fau = sa1 THEN
    > o1 <= ( (and_table(i1.log, i2.log) nand '1'), nofault);
    > ELSE
    > o1 <= ( (and_table(i1.log, i2.log) nand i3.log), nofault);
    > END IF;
    > END PROCESS;
    >
    >
    >
    > END dataflow;
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > USE WORK.problem_2.ALL;
    >
    >
    > -- ## XOR2
    >
    > ENTITY xor2 IS
    > PORT (i1, i2 : IN std_ulogic_faultable;
    > o1 : OUT std_ulogic_faultable);
    > END xor2;
    > --
    > ARCHITECTURE dataflow OF xor2 IS
    > BEGIN
    >
    > PROCESS (i1, i2)
    > BEGIN
    > IF i1.fau = sa0 THEN
    > o1 <= ('0' xor i2.log, nofault);
    > ELSIF i2.fau = sa0 THEN
    > o1 <= (i1.log xor '0', nofault);
    > ELSIF i1.fau = sa1 THEN
    > o1 <= ('1' xor i2.log, nofault);
    > ELSIF i2.fau = sa1 THEN
    > o1 <= (i1.log xor '1', nofault);
    > ELSE
    > o1 <= (i1.log xor i2.log, nofault);
    > END IF;
    > END PROCESS;
    >
    > END dataflow;
    >
    >
    >
    > ------------------------------------------------------------------------
    >
    > LIBRARY IEEE;
    > USE IEEE.std_logic_1164.ALL;
    > USE WORK.problem_2.ALL;
    >
    > -- ## Part d test
    > ENTITY part_d_test IS
    > END part_d_test;
    > --
    > ARCHITECTURE testbench OF part_d_test IS
    >
    > COMPONENT fourbitadder
    > GENERIC (faults : fault_array := (
    > -- example 0 => (0=> sa1, OTHERS => nofault),
    > 0 => (OTHERS => nofault),
    > 1 => (OTHERS => nofault),
    > 2 => (OTHERS => nofault),
    > 3 => (OTHERS => nofault)));
    >
    > PORT (a, b : IN sulog_fault_array (3 DOWNTO 0);
    > cin : IN std_ulogic_faultable;
    > sum : OUT sulog_fault_array (3 DOWNTO 0);
    > cout : OUT std_ulogic_faultable);
    >
    > END COMPONENT;
    >
    > FOR ALL: fourbitadder USE ENTITY WORK.fourbitadder(structural);
    >
    > SIGNAL a, b, sum : sulog_fault_array (3 DOWNTO 0);
    > SIGNAL cin, cout : std_ulogic_faultable;
    >
    > SIGNAL sum_log : std_ulogic_vector (3 DOWNTO 0);
    > SIGNAL a_log, b_log : std_ulogic_vector (3 DOWNTO 0) := "0000";
    > SIGNAL cin_log : std_ulogic := '0';
    > SIGNAL cout_log : std_ulogic ;
    >
    > SIGNAL a_fault, b_fault, sum_fault : fault_array(3 DOWNTO 0);
    >
    > SIGNAL aflt0, aflt1, aflt2, aflt3 : fault;
    > SIGNAL bflt0, bflt1, bflt2, bflt3 : fault;
    > SIGNAL sflt0, sflt1, sflt2, sflt3 : fault;
    > SIGNAL cin_fault, cout_fault : fault;
    >
    > BEGIN
    >
    > dut: fourbitadder GENERIC MAP (faults => (
    > 0 => (OTHERS => sa1),
    > 1 => (OTHERS => nofault),
    > 2 => (OTHERS => nofault),
    > 3 => (OTHERS => nofault)))
    > PORT MAP (a, b, cin, sum, cout);
    >
    > aflt0 <= a(0).fau;
    > aflt2 <= a(2).fau;
    > aflt1 <= a(1).fau;
    > aflt3 <= a(3).fau;
    > bflt0 <= b(0).fau;
    > bflt2 <= b(2).fau;
    > bflt1 <= b(1).fau;
    > bflt3 <= b(3).fau;
    > sflt0 <= sum(0).fau;
    > sflt2 <= sum(2).fau;
    > sflt1 <= sum(1).fau;
    > sflt3 <= sum(3).fau;
    >
    > cin_fault <= cin.fau;
    > cout_fault <= cout.fau;
    >
    > a_log(3 DOWNTO 0) <= (a(3).log, a(2).log, a(1).log, a(0).log);
    > b_log(3 DOWNTO 0) <= (b(3).log, b(2).log, b(1).log, b(0).log);
    > sum_log(3 DOWNTO 0) <= (sum(3).log, sum(2).log, sum(1).log, sum(0).log);
    > cout_log <= cout.log;
    >
    > PROCESS
    > BEGIN
    > cin.fau <= nofault;
    >
    > a(0).fau <= nofault;
    > a(1).fau <= nofault;
    > a(2).fau <= nofault;
    > a(3).fau <= nofault;
    >
    > b(0).fau <= nofault;
    > b(1).fau <= nofault;
    > b(2).fau <= nofault;
    > b(3).fau <= nofault;
    >
    >
    > -- actual sigs
    > cin.log <= '0';
    >
    > a(0).log <= '0';
    > a(1).log <= '0';
    > a(2).log <= '0';
    > a(3).log <= '0';
    >
    > b(0).log <= '0';
    > b(1).log <= '0';
    > b(2).log <= '0';
    > b(3).log <= '0';
    >
    > --cout.fau <= nofault;
    >
    > sum(0).fau <= nofault;
    > sum(1).fau <= nofault;
    > sum(2).fau <= nofault;
    > sum(3).fau <= nofault;
    > wait for 10 NS;
    > a(0).log <= '1';
    > wait for 10 NS;
    > b(0).log <= '1';
    > wait for 10 NS;
    > a(1).log <= '1';
    > a(0).log <= '0';
    > b(0).log <= '0';
    > wait for 10 NS;
    > b(0).log <= '1';
    > wait for 10 NS;
    > a(0).log <= '0';
    > wait for 10 NS;
    > a(0).log <= '1';
    > a(1).log <= '1';
    > a(2).log <= '1';
    > a(3).log <= '1';
    > b(0).log <= '0';
    > b(1).log <= '0';
    > b(2).log <= '0';
    > b(3).log <= '0';
    > WAIT FOR 10 NS;
    > b(0).log <= '1';
    > WAIT FOR 10 NS;
    >
    > WAIT;
    >
    > END PROCESS;
    >
    > END testbench;
     
    Dennis Shumaker, Aug 2, 2003
    #2
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  3. Pedro Claro

    FE Guest

    Re: compile error c0044: resolution is an undefined resolution function

    Hi Dennis,

    faulty_resolution2 is a resolution function of std_ulogic_faultable and not
    sulog_fault_array.

    So you should write,
    signal im : faulty_resolution2 std_ulogic_faultable;

    but im must be an array so what you want I think is something like that :
    subtype my_resolved_type is faulty_resolution2 std_ulogic_faultable;
    type my_resolved_type_array is array (natural range <>) of
    my_resolved_type;

    signal im : my_resolved_type_array(32 downto 0);

    regards
    FE


    "Dennis Shumaker" <> wrote in message
    news:...
    > I updated my email address..First post does not haev the correct email
    > address
    >
    > If someone doesn't know why I am getting the compile error, maybe
    > soemone could point me to understand what C0044 means? A error
    > definition book..that has more information.
    >
    > Thank you
    >
    > Dennis
    >
    > lid wrote:
    > > Hello
    > >
    > > I am getting a compile error on this line in the file fourbitadder.vhd
    > >
    > > SIGNAL im : faulty_resolution2 sulog_fault_array;
    > >
    > > C0044: faulty_resolution2 is an undefined resolution function
    > >
    > > I have no idea why it says that when it is clearly defined in the code
    > > only a few lines above it!
    > >
    > > Anyone know why I am getting this error message?
    > >
    > > Thank you in advance
    > >
    > > Dennis
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > >
    > > PACKAGE problem_2 IS
    > >
    > > TYPE fault IS (sa1, sa0, nofault);
    > >
    > > TYPE std_ulogic_faultable IS RECORD
    > > log : std_ulogic;
    > > fau : fault;
    > > END RECORD;
    > >
    > >
    > > TYPE stdlogic_table IS ARRAY (std_ulogic, std_ulogic) OF std_ulogic;
    > > CONSTANT resolution_table : stdlogic_table := (
    > > ------------------------------------------------------------
    > > --| U X 0 1 Z W L H - | |
    > > ------------------------------------------------------------
    > > ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
    > > ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
    > > ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
    > > ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
    > > ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
    > > ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
    > > ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |
    > >
    > >
    > > TYPE sulog_fault_array is ARRAY (NATURAL RANGE <>) OF

    std_ulogic_faultable ;
    > > -- TYPE sulog_fault_array is ARRAY (32 DOWNTO 0) OF

    std_ulogic_faultable ;
    > >
    > > FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN

    std_ulogic_faultable ;
    > >
    > > -- SUBTYPE wired_std_ulogic_faultable IS faulty_resolution

    std_ulogic_faultable;
    > >
    > > -- ##### Part D ######
    > > CONSTANT and_table : stdlogic_table := (
    > > ------------------------------------------------------------
    > > --| U X 0 1 Z W L H - | |
    > > ------------------------------------------------------------
    > > ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
    > > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
    > > ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
    > > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
    > > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
    > > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
    > > ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
    > > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
    > > ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )); -- | - |
    > >
    > >
    > > CONSTANT xor_table : stdlogic_table := (
    > > ------------------------------------------------------------
    > > --| U X 0 1 Z W L H - | |
    > > ------------------------------------------------------------
    > > ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
    > > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
    > > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
    > > ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
    > > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
    > > ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )); -- | - |
    > >
    > >
    > > TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
    > >
    > > CONSTANT not_table : stdlogic_1d :=
    > > ------------------------------------------------------------
    > > --| U X 0 1 Z W L H - | |
    > > ------------------------------------------------------------
    > > ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
    > >
    > >
    > > FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
    > > FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic;
    > >
    > >
    > >
    > > TYPE fault_vector IS ARRAY (8 DOWNTO 0) OF fault;
    > > TYPE fault_array IS ARRAY (3 DOWNTO 0) OF fault_vector;
    > >
    > > END problem_2;
    > >
    > > PACKAGE BODY problem_2 IS
    > >
    > >
    > > FUNCTION faulty_resolution (drivers : sulog_fault_array ) RETURN

    std_ulogic_faultable IS
    > > -- record std_ulogic_faultable = (log, fau)
    > > -- log = std_ulogic
    > > -- fau = (sa1, sa0, nofault)
    > >
    > > VARIABLE logic_temp : std_ulogic ;
    > > VARIABLE fault_temp : fault := nofault;
    > >
    > > BEGIN
    > >
    > > FOR i IN drivers'RANGE LOOP
    > >
    > > IF drivers(i).fau = sa0 THEN
    > > logic_temp := '0';
    > > fault_temp := sa0;
    > > EXIT;
    > > ELSIF drivers(i).fau = sa1 THEN
    > > logic_temp := '1';
    > > fault_temp := sa1;
    > > EXIT;
    > > ELSIF drivers(i).fau = nofault THEN
    > > logic_temp := resolution_table (logic_temp, drivers(i).log);
    > > fault_temp := drivers(i).fau;
    > > end IF;
    > >
    > > END LOOP;
    > >
    > > RETURN (logic_temp, fault_temp);
    > >
    > > END faulty_resolution;
    > >
    > > --####### Part D ######
    > >
    > > FUNCTION "nand" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
    > > variable temp : std_ulogic;
    > > BEGIN
    > >
    > > temp := and_table(l, r);
    > >
    > > RETURN not_table(temp);
    > >
    > > END "nand";
    > >
    > >
    > > FUNCTION "xor" (l : std_ulogic; r : std_ulogic) RETURN std_ulogic IS
    > > BEGIN
    > >
    > > RETURN xor_table (l, r);
    > >
    > > END "xor";
    > >
    > > END problem_2 ;
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > > USE WORK.problem_2.ALL;
    > > --
    > > --
    > > -- ## 4-bit Adder
    > > ENTITY fourbitadder IS
    > > GENERIC (faults : fault_array := (
    > > 0 => (0=> sa1, OTHERS => sa0),
    > > -- 0 => (OTHERS => nofault),
    > > 1 => (OTHERS => nofault),
    > > 2 => (OTHERS => nofault),
    > > 3 => (OTHERS => nofault)));
    > >
    > > PORT (a, b : IN sulog_fault_array(3 DOWNTO 0);
    > > cin : IN std_ulogic_faultable;
    > > sum : OUT sulog_fault_array(3 DOWNTO 0);
    > > cout : OUT std_ulogic_faultable);
    > >
    > > END fourbitadder;
    > > --
    > > ARCHITECTURE structural OF fourbitadder IS
    > >
    > > FUNCTION faulty_resolution2 (drivers : sulog_fault_array ) RETURN

    std_ulogic_faultable IS
    > > -- record std_ulogic_faultable = (log, fau)
    > > -- log = std_ulogic
    > > -- fau = (sa1, sa0, nofault)
    > >
    > > VARIABLE logic_temp : std_ulogic ;
    > > VARIABLE fault_temp : fault := nofault;
    > > VARIABLE temp_comb : std_ulogic_faultable;
    > >
    > > BEGIN
    > >
    > > FOR i IN drivers'RANGE LOOP
    > >
    > > IF drivers(i).fau = sa0 THEN
    > > logic_temp := '0';
    > > fault_temp := sa0;
    > > EXIT;
    > > ELSIF drivers(i).fau = sa1 THEN
    > > logic_temp := '1';
    > > fault_temp := sa1;
    > > EXIT;
    > > ELSIF drivers(i).fau = nofault THEN
    > > logic_temp := resolution_table (logic_temp, drivers(i).log);
    > > fault_temp := drivers(i).fau;
    > > end IF;
    > >
    > > END LOOP;
    > > temp_comb := (logic_temp, fault_temp);
    > >
    > > RETURN temp_comb;
    > >
    > > END faulty_resolution2;
    > >
    > > --SUBTYPE fault_res IS faulty_resolution std_ulogic_faultable ;
    > > --TYPE fault_res_array IS ARRAY (32 DOWNTO 0) OF fault_res;
    > >
    > > COMPONENT xor2
    > > PORT (i1, i2 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > > END COMPONENT;
    > > COMPONENT nand2
    > > PORT (i1, i2 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > > END COMPONENT;
    > > COMPONENT nand3
    > > PORT (i1, i2, i3 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > > END COMPONENT;
    > >
    > >
    > >
    > > SIGNAL im : faulty_resolution2 sulog_fault_array;
    > >
    > >
    > > BEGIN
    > > im(0) <= cin;
    > > -- fulladders
    > >
    > > iti : FOR i IN 0 TO 3 GENERATE
    > > -- wires of each fulladder
    > >
    > > itj : FOR j IN 0 TO 8 GENERATE
    > > -- inject fault
    > > im(i*8+j).fau <= faults(i)(j);
    > > im(i*8+j).log <= '0' WHEN (faults(i)(j) = sa0) ELSE
    > > '1' WHEN (faults(i)(j) = sa1) ELSE 'Z';
    > > END GENERATE;
    > >
    > > --fulladder
    > > im(i*8+1) <= a(i);
    > > im(i*8+2) <= b(i);
    > > x1 : xor2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+3));
    > > x2 : xor2 PORT MAP (im(i*8), im(i*8+3), im(i*8+7));
    > > n1 : nand2 PORT MAP (im(i*8+1), im(i*8+2), im(i*8+4));
    > > n2 : nand2 PORT MAP (im(i*8), im(i*8+1), im(i*8+5));
    > > n3 : nand2 PORT MAP (im(i*8), im(i*8+2), im(i*8+6));
    > > n4 : nand3 PORT MAP (im(i*8+4), im(i*8+5), im(i*8+6), im((i+1)*8));
    > > sum(i) <= im(i*8+7);
    > > END GENERATE;
    > >
    > > cout <= im(32);
    > >
    > > END structural;
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > > USE WORK.problem_2.ALL;
    > >
    > > ENTITY nand2 IS
    > >
    > > PORT (i1, i2 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > >
    > > END nand2;
    > > --
    > > ARCHITECTURE dataflow OF nand2 IS
    > >
    > > BEGIN
    > >
    > > PROCESS (i1, i2)
    > > BEGIN
    > > IF i1.fau = sa0 OR i2.fau = sa0 THEN
    > > o1 <= ('1', nofault);
    > > ELSIF i1.fau = sa1 THEN
    > > o1 <= (('1' nand i2.log), nofault);
    > > ELSIF i2.fau = sa1 THEN
    > > o1 <= ((i1.log nand '1'), nofault);
    > > ELSE
    > > o1 <= (( i1.log nand i2.log), nofault);
    > > END IF;
    > > END PROCESS;
    > >
    > > END dataflow;
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > > USE WORK.problem_2.ALL;
    > >
    > > ENTITY nand3 IS
    > >
    > > PORT (i1, i2, i3 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > >
    > > END nand3;
    > > --
    > > ARCHITECTURE dataflow OF nand3 IS
    > >
    > > BEGIN
    > >
    > > PROCESS (i1, i2, i3)
    > > BEGIN
    > > IF i1.fau = sa0 OR i2.fau = sa0 OR i3.fau = sa0 THEN
    > > o1 <= ('1', nofault);
    > > ELSIF i1.fau = sa1 THEN
    > > o1 <= ( (and_table('1',i2.log) nand i3.log), nofault);
    > > ELSIF i2.fau = sa1 THEN
    > > o1 <= ( (and_table(i1.log, '1') nand i3.log), nofault);
    > > ELSIF i3.fau = sa1 THEN
    > > o1 <= ( (and_table(i1.log, i2.log) nand '1'), nofault);
    > > ELSE
    > > o1 <= ( (and_table(i1.log, i2.log) nand i3.log), nofault);
    > > END IF;
    > > END PROCESS;
    > >
    > >
    > >
    > > END dataflow;
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > > USE WORK.problem_2.ALL;
    > >
    > >
    > > -- ## XOR2
    > >
    > > ENTITY xor2 IS
    > > PORT (i1, i2 : IN std_ulogic_faultable;
    > > o1 : OUT std_ulogic_faultable);
    > > END xor2;
    > > --
    > > ARCHITECTURE dataflow OF xor2 IS
    > > BEGIN
    > >
    > > PROCESS (i1, i2)
    > > BEGIN
    > > IF i1.fau = sa0 THEN
    > > o1 <= ('0' xor i2.log, nofault);
    > > ELSIF i2.fau = sa0 THEN
    > > o1 <= (i1.log xor '0', nofault);
    > > ELSIF i1.fau = sa1 THEN
    > > o1 <= ('1' xor i2.log, nofault);
    > > ELSIF i2.fau = sa1 THEN
    > > o1 <= (i1.log xor '1', nofault);
    > > ELSE
    > > o1 <= (i1.log xor i2.log, nofault);
    > > END IF;
    > > END PROCESS;
    > >
    > > END dataflow;
    > >
    > >
    > >
    > > ------------------------------------------------------------------------
    > >
    > > LIBRARY IEEE;
    > > USE IEEE.std_logic_1164.ALL;
    > > USE WORK.problem_2.ALL;
    > >
    > > -- ## Part d test
    > > ENTITY part_d_test IS
    > > END part_d_test;
    > > --
    > > ARCHITECTURE testbench OF part_d_test IS
    > >
    > > COMPONENT fourbitadder
    > > GENERIC (faults : fault_array := (
    > > -- example 0 => (0=> sa1, OTHERS => nofault),
    > > 0 => (OTHERS => nofault),
    > > 1 => (OTHERS => nofault),
    > > 2 => (OTHERS => nofault),
    > > 3 => (OTHERS => nofault)));
    > >
    > > PORT (a, b : IN sulog_fault_array (3 DOWNTO 0);
    > > cin : IN std_ulogic_faultable;
    > > sum : OUT sulog_fault_array (3 DOWNTO 0);
    > > cout : OUT std_ulogic_faultable);
    > >
    > > END COMPONENT;
    > >
    > > FOR ALL: fourbitadder USE ENTITY WORK.fourbitadder(structural);
    > >
    > > SIGNAL a, b, sum : sulog_fault_array (3 DOWNTO 0);
    > > SIGNAL cin, cout : std_ulogic_faultable;
    > >
    > > SIGNAL sum_log : std_ulogic_vector (3 DOWNTO 0);
    > > SIGNAL a_log, b_log : std_ulogic_vector (3 DOWNTO 0) := "0000";
    > > SIGNAL cin_log : std_ulogic := '0';
    > > SIGNAL cout_log : std_ulogic ;
    > >
    > > SIGNAL a_fault, b_fault, sum_fault : fault_array(3 DOWNTO 0);
    > >
    > > SIGNAL aflt0, aflt1, aflt2, aflt3 : fault;
    > > SIGNAL bflt0, bflt1, bflt2, bflt3 : fault;
    > > SIGNAL sflt0, sflt1, sflt2, sflt3 : fault;
    > > SIGNAL cin_fault, cout_fault : fault;
    > >
    > > BEGIN
    > >
    > > dut: fourbitadder GENERIC MAP (faults => (
    > > 0 => (OTHERS => sa1),
    > > 1 => (OTHERS => nofault),
    > > 2 => (OTHERS => nofault),
    > > 3 => (OTHERS => nofault)))
    > > PORT MAP (a, b, cin, sum, cout);
    > >
    > > aflt0 <= a(0).fau;
    > > aflt2 <= a(2).fau;
    > > aflt1 <= a(1).fau;
    > > aflt3 <= a(3).fau;
    > > bflt0 <= b(0).fau;
    > > bflt2 <= b(2).fau;
    > > bflt1 <= b(1).fau;
    > > bflt3 <= b(3).fau;
    > > sflt0 <= sum(0).fau;
    > > sflt2 <= sum(2).fau;
    > > sflt1 <= sum(1).fau;
    > > sflt3 <= sum(3).fau;
    > >
    > > cin_fault <= cin.fau;
    > > cout_fault <= cout.fau;
    > >
    > > a_log(3 DOWNTO 0) <= (a(3).log, a(2).log, a(1).log, a(0).log);
    > > b_log(3 DOWNTO 0) <= (b(3).log, b(2).log, b(1).log, b(0).log);
    > > sum_log(3 DOWNTO 0) <= (sum(3).log, sum(2).log, sum(1).log, sum(0).log);
    > > cout_log <= cout.log;
    > >
    > > PROCESS
    > > BEGIN
    > > cin.fau <= nofault;
    > >
    > > a(0).fau <= nofault;
    > > a(1).fau <= nofault;
    > > a(2).fau <= nofault;
    > > a(3).fau <= nofault;
    > >
    > > b(0).fau <= nofault;
    > > b(1).fau <= nofault;
    > > b(2).fau <= nofault;
    > > b(3).fau <= nofault;
    > >
    > >
    > > -- actual sigs
    > > cin.log <= '0';
    > >
    > > a(0).log <= '0';
    > > a(1).log <= '0';
    > > a(2).log <= '0';
    > > a(3).log <= '0';
    > >
    > > b(0).log <= '0';
    > > b(1).log <= '0';
    > > b(2).log <= '0';
    > > b(3).log <= '0';
    > >
    > > --cout.fau <= nofault;
    > >
    > > sum(0).fau <= nofault;
    > > sum(1).fau <= nofault;
    > > sum(2).fau <= nofault;
    > > sum(3).fau <= nofault;
    > > wait for 10 NS;
    > > a(0).log <= '1';
    > > wait for 10 NS;
    > > b(0).log <= '1';
    > > wait for 10 NS;
    > > a(1).log <= '1';
    > > a(0).log <= '0';
    > > b(0).log <= '0';
    > > wait for 10 NS;
    > > b(0).log <= '1';
    > > wait for 10 NS;
    > > a(0).log <= '0';
    > > wait for 10 NS;
    > > a(0).log <= '1';
    > > a(1).log <= '1';
    > > a(2).log <= '1';
    > > a(3).log <= '1';
    > > b(0).log <= '0';
    > > b(1).log <= '0';
    > > b(2).log <= '0';
    > > b(3).log <= '0';
    > > WAIT FOR 10 NS;
    > > b(0).log <= '1';
    > > WAIT FOR 10 NS;
    > >
    > > WAIT;
    > >
    > > END PROCESS;
    > >
    > > END testbench;

    >
     
    FE, Aug 2, 2003
    #3
  4. Re: compile error c0044: resolution is an undefined resolution function

    lid wrote:

    > SIGNAL im : faulty_resolution2 sulog_fault_array;
    >
    > C0044: faulty_resolution2 is an undefined resolution function
    >
    > I have no idea why it says that when it is clearly defined in the code
    > only a few lines above it!



    Sometimes the compiler message misses the first error, which
    in this case may be that faulty_resolution2 failed to compile
    and maybe that is why it is undefined.

    Consider testing just faulty_resolution2 with a simpler testbench.

    -- Mike Treseler
     
    Mike Treseler, Aug 3, 2003
    #4
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