Re: Type Conversion in Association List

Discussion in 'VHDL' started by MK, Aug 1, 2003.

  1. MK

    MK Guest

    You should use conversion on formal, because c1 is output port - it must
    looks like:

    to_stdulogic(c1) => c1

    regards,
    MK.


    "Anand P Paralkar" <> wrote in message
    news:p...
    > Hi,
    >
    > I am trying to instantiate an entity within an architecture. The entity
    > ports are of type bit and the signals in the architecture, to which these
    > ports must be associated are of type std_logic. How do I interface ports
    > of mode "out" and type "bit" with signals that are of type "std_logic".
    >
    > I have given an example below. Please go through it and the queries below
    > if you have the time. This would help me in making my point clear.
    >
    > Thanks,
    > Anand
    >
    > --------------------------------------------------------------------------

    -----
    > Example
    > --------------------------------------------------------------------------

    -----
    > Description
    > --------------------------------------------------------------------------

    -----
    > cla_gen : The cla_gen entity and architecture form the combinational logic
    > model for a carry look ahead logic.
    >
    > cla_16b : The cla_16b entity and architecture form the structural model
    > for a carry look ahead based 16 bit adder. The architecture
    > also instantiates a cla based 4 bit adder; The code for which
    > is not given below.
    >
    > The architecture of the cla_16b (with std_logic signals) instantiates
    > cla_gen whose ports are of type bit.
    > --------------------------------------------------------------------------

    -----
    > Code
    > --------------------------------------------------------------------------

    -----
    > library ieee; use ieee.std_logic_1164.all;
    >
    > entity cla_gen is
    > port (p0, p1, p2, p3, g0, g1, g2, g3, c_in : in bit;
    > c1, c2, c3 : out bit);
    > end entity cla_gen;
    >
    > architecture combo of cla_gen is
    > begin
    > c1 <= g0 or (p0 and c_in);
    > c2 <= g1 or (p1 and (g0 or (p0 and c_in)));
    > c3 <= g2 or (p2 and (g1 or (p1 and (g0 or (p0 and c_in)))));
    > end architecture combo;
    >
    > library ieee; use ieee.std_logic_1164.all;
    >
    > entity cla_16b is
    > port (a, b : in std_logic_vector (15 downto 0);
    > s : out std_logic_vector (15 downto 0);
    > c_in : in std_logic;
    > c_out : out std_logic);
    > end entity cla_16b;
    >
    > architecture struct of cla_16b is
    > signal g0, g1, g2, g3, p0, p1, p2, p3, c1, c2, c3 : std_logic;
    > begin
    >
    > nib0 : entity work.cla(combo)
    > port map(a(3 downto 0), b(3 downto 0), c_in, s(3 downto 0),
    > open, g0, p0);
    >
    > nib1 : entity work.cla(combo)
    > port map(a(7 downto 4), b(7 downto 4), c1, s(7 downto 4),
    > open, g1, p1);
    >
    > nib2 : entity work.cla(combo)
    > port map(a(11 downto 8), b(11 downto 8), c1, s(11 downto 8),
    > open, g2, p2);
    >
    > nib3 : entity work.cla(combo)
    > port map(a(15 downto 12), b(15 downto 12), c1, s(15 downto 12),
    > open, g3, p3);
    >
    > cla_gen : entity work.cla_gen(combo)
    > port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
    > to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
    > to_bit(c_in),
    > c1 => ??, c2 => ??,
    > c3 => ??);
    >
    > end architecture struct;
    > --------------------------------------------------------------------------

    -----
    > Queries
    > --------------------------------------------------------------------------

    -----
    > 1. What do I write in place of the "??" above?
    >
    > 2. I have tried writing:
    >
    > c1 => to_stdulogic(c1)
    > | |
    > std_logic bit signal
    > signal of of cla_gen
    > cla_16b
    >
    > However, the compiler (ncvhdl) returns a message:
    >
    > subprogram call or operator argument type mismatch.
    >
    > This probably means that the to_stdulogic call is not interpreting
    > its argument correctly.
    >
    > --------------------------------------------------------------------------

    -----
    >
    > Thank you for your time.
    >
    > Thanks,
    > Anand
    >
     
    MK, Aug 1, 2003
    #1
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  2. MK,

    I tried that, now the compiler returns an error on the input port.

    That is in the instantiation:

    cla_gen : entity work.cla_gen(combo)
    port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
    to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
    to_bit(c_in), to_stdulogic(c1) => c1,
    to_stdulogic(c2) => c2, to_stdulogic(c3) => c3);

    It reports an error as follows:

    port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
    |
    illegal type conversion function

    Thanks for your reply.

    Thanks,
    Anand
     
    Anand P Paralkar, Aug 1, 2003
    #2
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  3. MK

    MK Guest

    This is because function to_bit has 2 input formal parameters (one is
    optional), so it not allowed as conversion function. You need write simple
    wrapper:

    function my_to_bit(p: std_ulogic) return bit is
    begin
    return to_bit(p);
    end;

    and use my_to_bit instead of to_bit in port map.

    good luck :)
    MK.

    "Anand P Paralkar" <> wrote in message
    news:p...
    > MK,
    >
    > I tried that, now the compiler returns an error on the input port.
    >
    > That is in the instantiation:
    >
    > cla_gen : entity work.cla_gen(combo)
    > port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
    > to_bit(g0), to_bit(g1), to_bit(g2), to_bit(g3),
    > to_bit(c_in), to_stdulogic(c1) => c1,
    > to_stdulogic(c2) => c2, to_stdulogic(c3) => c3);
    >
    > It reports an error as follows:
    >
    > port map(to_bit(p0), to_bit(p1), to_bit(p2), to_bit(p3),
    > |
    > illegal type conversion function
    >
    > Thanks for your reply.
    >
    > Thanks,
    > Anand
    >
     
    MK, Aug 1, 2003
    #3
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