Re: unused input ports

Discussion in 'VHDL' started by Mario Trams, Jul 22, 2003.

  1. Mario Trams

    Mario Trams Guest

    Bob wrote:

    > Hi,
    >
    > I am passing in a signal to a component. The signal is not used
    > but I want to keep it there to have uniformity with other very similar
    > components. Synthesis gives me a warning, which I would like to
    > remove.
    >
    > Do you know of any way that I can remove the warning while still
    > keeping the input port ?


    Hi Bob,

    just attach a dummy signal to these ports.
    I usually have two signals "high" and "low" that always keep a
    '1' or a '0' for such purposes.

    Btw., I don't know your design in detail, but leaving inputs
    open might cause errors in the later stages of synthesis.

    Regards,
    Mario
    Mario Trams, Jul 22, 2003
    #1
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