Re: VHDL and Sin

Discussion in 'VHDL' started by Jonathan Bromley, Feb 3, 2011.

  1. On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

    See the other responses.

    I love the subject line. Sin in VHDL, repent in Verilog?
    --
    Jonathan Bromley
     
    Jonathan Bromley, Feb 3, 2011
    #1
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  2. Jonathan Bromley

    rickman Guest

    On Feb 3, 4:39 pm, Jonathan Bromley <>
    wrote:
    > On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:
    >
    > See the other responses.
    >
    > I love the subject line.  Sin in VHDL, repent in Verilog?
    > --
    > Jonathan Bromley


    LOL!
     
    rickman, Feb 4, 2011
    #2
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  3. Jonathan Bromley

    Andy Guest

    On Feb 3, 3:39 pm, Jonathan Bromley <>
    wrote:
    > On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:
    >
    > See the other responses.
    >
    > I love the subject line.  Sin in VHDL, repent in Verilog?
    > --
    > Jonathan Bromley


    Well, there's original sin(), concurrent sin(), sequential (serial?)
    sin(), procedural sin(), functional sin()

    Let's not forget monadic err... unary sin() and dyadic sin().

    Or just "Go Forth and sin() no more."

    Andy
     
    Andy, Feb 7, 2011
    #3
  4. On Mon, 7 Feb 2011 10:39:38 -0800 (PST), Andy wrote:

    >dyadic sin()


    That's co-sin, right?

    Jonathan Bromley
     
    Jonathan Bromley, Feb 7, 2011
    #4
  5. Jonathan Bromley

    KJ Guest

    On Feb 7, 4:42 pm, Jonathan Bromley <>
    wrote:
    > On Mon, 7 Feb 2011 10:39:38 -0800 (PST), Andy wrote:
    > >dyadic sin()

    >
    > That's co-sin, right?
    >
    > Jonathan Bromley


    You two really should get off this tangent.

    KJ
     
    KJ, Feb 7, 2011
    #5
  6. Jonathan Bromley

    Tricky Guest

    On Feb 8, 10:20 am, tommy <> wrote:
    > Il 07/02/2011 19:39, Andy ha scritto:
    >
    >
    >
    > > On Feb 3, 3:39 pm, Jonathan Bromley<>
    > > wrote:
    > >> On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote:

    >
    > >> See the other responses.

    >
    > >> I love the subject line.  Sin in VHDL, repent in Verilog?
    > >> --
    > >> Jonathan Bromley

    >
    > > Well, there's original sin(), concurrent sin(), sequential (serial?)
    > > sin(), procedural sin(), functional sin()

    >
    > > Let's not forget monadic err... unary sin() and dyadic sin().

    >
    > > Or just "Go Forth and sin() no more."

    >
    > > Andy

    >
    > I need to write an entity  for the approximate calculation of e^sin (x)
    > where x is a number representation in fixed point 2's complement, and |
    > x | <3.14 / 2.
    >
    > my entity will be like this:
    >
    >   exp_sin_x entity is
    >   port (x: in signed (15 downto 0), y: out signed (15 downto 0),
    >   clk: in std_ulogic)
    >   end entity;
    >
    >   where the type is defined in the package signed IEEE / numeric_std, x
    > must be interpreted as a fixed point number format Q3.13 (i.e. x between
    > -4 and +4) and y as a fixed point number format with Q3.13 (then y lies
    > between -4 and +4)), clk is a clock signal to synchronize operations.
    >
    > First I need a behavioral model and test it with a suitable test-bench.
    > Then I have to write a synthesizable RTL model is tested by comparing
    > the behavioral model.
    >
    > I can approximate both the behavioral and structural model with:
    >
    >   e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x
    > ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6
    >
    > (in the structural relationship, the coefficients are processed in fixed
    > point and the polynomial is calculated using fixed-point operations).
    >
    > thanks again in advance


    First of all, why not look into the new IEEE fixed point package. For
    VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/

    Then you can do nice things like:

    port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc

    So the bit numbers represent the real powers of 2 in the fixed point
    numbers.

    Then for a behavioural model, you can do this:

    use ieee.math_real.all;
    ....
    port (clk : in std_logic;
    x: in sfixed (2 downto -13);
    y: out sfixed(2 downto -13));
    .....
    process
    variable x_rl : real;
    variable y_rl : real;
    begin
    wait until rising_edge(clk);
    x_rl := to_real(x);
    y_rl := math_e ** sin(x_rl);
    y <= to_sfixed(y_rl, y'high, y'low);
    end process;

    This wont be synthesisable, but it is a nice simple behavioural model.
    For a synthesisable implementation, a look up table is usually the
    best approach, but at 16 bits thats a fair chunk of memory!
     
    Tricky, Feb 8, 2011
    #6
  7. Jonathan Bromley

    HT-Lab Guest

    "tommy" wrote in message
    news:4d524d36$0$1367$...

    >Il 08/02/2011 17:55, Tricky ha scritto:
    >..>
    >> This wont be synthesisable, but it is a nice simple behavioural model.
    >> For a synthesisable implementation, a look up table is usually the
    >> best approach, but at 16 bits thats a fair chunk of memory!

    >
    >This is nice approach but i need help for synthesisable codes... how can I
    >develop this ?


    As Tricky and and others wrote, go for Cordic or look-up table approach.
    There are lots of Cordic examples on the web, this paper might also help:

    http://www.ht-lab.com/misc/papers/paper_mapld_6.pdf

    If you want to use a LUT then try to find a paper by Robert Sutherland which
    describes a method of using two much smaller look-up tables. I can't
    remember all the details but a picture of the architecture is on slide 16
    here:

    http://klabs.org/richcontent/MAPLDCon99/Presentations/A2_Vladimirova_S.pdf

    Hans
    www.ht-lab.com
     
    HT-Lab, Feb 9, 2011
    #7
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