Re: vhdl and ultraedit

Discussion in 'VHDL' started by Andy, Apr 24, 2007.

  1. Andy

    Andy Guest

    On Apr 23, 4:27 pm, "mans" <(myname_here)> wrote:
    > Hello,
    > I decided to test UltraEdit to see how good is it in reformatting a
    > VHDL code and indenting smartly. To do this I installed ultraedit and I did
    > a test by asking UE to reformat this code for me:
    >
    > process (Rst)
    > begin
    > if clk='1' then
    >
    > if Rst='1' then system_state <= wait_for_input;
    >
    > end if;
    > end if;
    > end process;
    >
    > and I got this:
    >
    > process (Rst) begin if clk='1' then
    >
    > if Rst='1' then system_state <= wait_for_input;
    >
    > end if; end if; end process;
    >
    > which I think is not a good reformatting.
    >
    > My question is:
    >
    > Can UE reformat VHDL code and doing the smart indentation on it?
    > Is the result that I am getting correct?
    > Am I missing anything?
    > My search on the web showed that I should get a new file for this, Am I
    > right? Where can I get it?
    >
    > Regards


    I generally prefer xemacs or jgrasp for vhdl editors (both free).
    xemacs' beautification is peerless. Getting it set up to be more PC-
    friendly is not easy though. Jgrasp has very good indenting and
    highlighting capabilities, and can insert graphical structural cues in
    the whitespace in the left margin.

    Smart indenting in UE is somewhat limited by the way it is configured.
    I decided to start over with their ada mode, and go from there. The
    following generally works pretty well, but does have some issues. Most
    glaring is that process statement lines must either begin with
    "process" or end with "is" (optional keyword in vhdl). If you have a
    label for the process, put it on the previous line. Ignore the
    Function String lines, I couldn't get them to work right. Indenting is
    controlled by the /Indent Strings, /Indent Strings SOL (start of
    line), and /Unindent Strings records.

    /L20"VHDL" Line Comment = -- Nocase String Chars = " File Extensions
    = VHD VHO VHDL
    /Delimiters = ; ( )'<>=:+-/*|&
    /Indent Strings = "then" "loop" "is" "generate" "begin" "else"
    "record"
    /Indent Strings SOL = "when " "process " "postponed " "component "
    "block " "for " "units "
    /Unindent Strings = "end " "elsif" "when" "begin" "else"
    /Function String 1 = "^(%[ ^t]++process[ ^t]++*$^)"
    /Function String 2 = "^(%*[ ^t]++IS[ ^t]++*$^)"
    /C1"VHDL reserved words"
    ABS ACCESS AFTER ALIAS ALL AND ARCHITECTURE ARRAY ASSERT ATTRIBUTE
    BEGIN BLOCK BODY BUFFER BUS
    CASE COMPONENT CONFIGURATION CONSTANT
    DISCONNECT DOWNTO
    ELSE ELSIF END ENTITY EXIT
    FILE FOR FUNCTION
    GENERATE GENERIC GROUP GUARDED
    IF IMPURE IN INERTIAL INOUT IS
    LABEL LIBRARY LINKAGE LITERAL LOOP
    MAP MOD
    NAND NEW NEXT NOR NOT NULL
    OF ON OPEN OR OTHERS OUT
    PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE
    RANGE RECORD REGISTER REJECT REM REPORT RETURN ROL ROR
    SELECT SEVERITY SIGNAL SHARED SLA SLL SRA SRL SUBTYPE
    THEN TO TRANSPORT TYPE
    UNAFFECTED UNITS UNTIL USE
    VARIABLE
    WAIT WHEN WHILE WITH
    XNOR XOR
    /C2"VHDL attributes"
    'active
    'ascending
    'base
    'delayed
    'driving
    'driving_value
    'event
    'high
    'image
    'instance_name
    'last_active
    'last_event
    'last_value
    'left leftof
    'length
    'low
    'path_name
    'pos pred
    'quiet
    'range
    'reverse_range
    'right rightof
    'simple_name
    'stable
    'succ
    'transaction
    'val
    'value
    /C3"VHDL strings"
    "
    /C4"VHDL types"
    bit bit_vector boolean
    character
    integer
    line
    natural
    positive
    real
    signed std_logic std_logic_vector string
    text time
    unsigned
     
    Andy, Apr 24, 2007
    #1
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  2. Andy <> writes:

    > I generally prefer xemacs or jgrasp for vhdl editors (both free).
    > xemacs' beautification is peerless. Getting it set up to be more PC-
    > friendly is not easy though.


    I agree about (x)emacs vhdl-mode, and it has many many more features
    as well. The copy entity, paste as a testbench (or signals, or
    instance etc...) is one of my favourites. And the TAB-completion of
    anything that comes to hand. Makes using long descriptive signal
    names painless.

    And... this makes it a lot easier on windows users:
    http://www.ourcomments.org/Emacs/EmacsW32.html

    Cheers,
    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.net/electronics.html
     
    Martin Thompson, Apr 25, 2007
    #2
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  3. Andy

    magician

    Joined:
    Oct 9, 2009
    Messages:
    1
    RJ Text editor is a good free alternative also
     
    magician, Oct 9, 2009
    #3
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