Re: VHDL sound generator

Discussion in 'VHDL' started by Nicholas Paul Collin Gloucester, Apr 6, 2012.

  1. On March 28th, 2012, Doubler <> sent:

    |--------------------------------------------------------------------------------------------------------------------|
    |"hello all. |
    |I have to make a VHDL sound generator using SPKR1 module. Can you give me some ideas how should I do this? Thnk you"|
    |--------------------------------------------------------------------------------------------------------------------|

    VHDL has no notion of "SPKR1 module". Perhaps this university problem
    is for a particular evaluation board or other kit in a laboratory in
    the university, and perhaps something called SPKR1 has been declared
    for you, which controls a speaker.

    We do not have the documentation for this. You do.

    Perhaps changing the value assigned to SPKR1 from '0' to '1' or vice
    versa would create a noise. Is any sound acceptable? Then maybe play
    with it, deciding how often you will toggle the speaker by trying it.
    Nicholas Paul Collin Gloucester, Apr 6, 2012
    #1
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