Re: vhdl UART

Discussion in 'VHDL' started by Mike Treseler, Aug 8, 2003.

  1. SneakerNet wrote:

    > The receive module of the uart has these I/Os:
    > clock: input
    > baudclock: input
    > RxD: input
    > Data_FromPC[7..0]: output




    That would be Data_To_PC




    > RxComplete: output
    >
    > The I/O's are self-explanatory.
    > Now how can i use the RxComplete signal to implement the buffer? Help. Any
    > info/advice appreciated.





    1 8 8
    RxD]---[UART]---/--[FIFO]--/---[Data_To_PC



    -- Mike Treseler
     
    Mike Treseler, Aug 8, 2003
    #1
    1. Advertising

  2. Mike Treseler

    SneakerNet Guest

    Hi Mike..

    I would like to point out that this is a receiver module (Rx) so what I
    wrote was correct. It is Data_FromPc[7..0] as it is a uart module that
    receives data from PC and sends it to other modules within FPGA. I don't
    know how you got the idea that it is Data_To_PC!.

    Anyway I have no idea what your reply means. Can you pls be more clear in
    this area.

    Cheers


    "Mike Treseler" <> wrote in message
    news:...
    > SneakerNet wrote:
    >
    > > The receive module of the uart has these I/Os:
    > > clock: input
    > > baudclock: input
    > > RxD: input
    > > Data_FromPC[7..0]: output

    >
    >
    >
    > That would be Data_To_PC
    >
    >
    >
    >
    > > RxComplete: output
    > >
    > > The I/O's are self-explanatory.
    > > Now how can i use the RxComplete signal to implement the buffer? Help.

    Any
    > > info/advice appreciated.

    >
    >
    >
    >
    > 1 8 8
    > RxD]---[UART]---/--[FIFO]--/---[Data_To_PC
    >
    >
    >
    > -- Mike Treseler
    >
     
    SneakerNet, Aug 10, 2003
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Anand P Paralkar

    UART Implementation

    Anand P Paralkar, Jun 26, 2003, in forum: VHDL
    Replies:
    2
    Views:
    13,030
    Rudolf Usselmann
    Jul 7, 2003
  2. Shashi

    Issues on clockless UART

    Shashi, Apr 21, 2004, in forum: VHDL
    Replies:
    3
    Views:
    714
  3. Shashi
    Replies:
    0
    Views:
    636
    Shashi
    Apr 21, 2004
  4. Konstantin Dols

    UART receiver

    Konstantin Dols, Dec 12, 2004, in forum: VHDL
    Replies:
    0
    Views:
    3,091
    Konstantin Dols
    Dec 12, 2004
  5. Neil

    Uart and clock

    Neil, Jun 25, 2005, in forum: VHDL
    Replies:
    1
    Views:
    666
    Dave Higton
    Jun 25, 2005
Loading...

Share This Page