Re: VHDLisms

Discussion in 'VHDL' started by Egbert Molenkamp, Aug 18, 2003.

  1. "William Wallace" <> wrote in message
    news:...
    > 1. Is there a general rule I can use to know when I need to use the
    > word "is" and when I do not? Also, what good does making somebody
    > type these two characters do?


    The syntax of VHDL is more or less based on ADA. The 'is' occurs also
    in ADA (I think).
    In the first VHDL standard (from 1987) the usage of 'is' is not consequent.
    E.g. ENTITY name IS
    but not
    COMPONENT name .. and NOT followed with 'is'

    From 1993 the syntax is more regular. At the places you (may) expect an
    'is' is allowed ('allowed' to be compatbile with '87 description).
    So nowadays you may also write:
    COMPONENT name IS ..

    Probably most of the tools support the '93 standard, there are of course
    many books that use the '87 style.

    What is the meaning of 'is' .. I think that it is only sugar (and probably
    only
    there because is was used in ADA?) But I'm not sure here.


    > 2. Is there a general rule I can use to figure out when two words are
    > combined into one word (e.g., "elsif") versus being kept as two words
    > (e.g., "end if")?


    IF cond1 THEN
    ...
    ELSE IF condi2 THEN
    ..
    END IF
    END IF;

    In the previous description "ELSE IF" can not be replaced with ELSIF.
    In the previous description there are TWO IF-statements. Where the
    ELSIF will result in ONE IF-statement. See next example (not the missing
    END IF).


    IF cond1 THEN
    ...
    ELSIF condi2 THEN
    ..
    END IF;

    (probably ELSEIF is not nice so therefore ELSIF is used)

    Furthermore END <..> is rather regular (also from VHD'93)
    ENTITY .. END ENTITY
    PROCESS .. END PROCESS
    IF .. END IF;
    CASE .. END CASE
    BLOCK .. END BLOCK
    etc.

    > 3. Is there a general rule I can use to figure out when I need to put
    > a semicolon (e.g., after the generic section and also the port section
    > in the component declaration) and when I do not (e.g., not after the
    > generic section but only after a port section of an instantiation)?

    I must confess. When I read the Peter Ashendens "The VHDL Cookbook"
    (in 1990 or so) I send him an email because I though he made an
    error with missing semicolums. I was wrong.

    > 4. Why if I pass a argument, say a std_logic_vector, to a function
    > that takes a std_logic_vector, do I need to use data_in(arg'low) in
    > the function as opposed to data_in(0). Why doesn't VHDL automatically
    > rejustify a function call, say, function(data(15 downto 8)) to
    > data_in(7 downto 0) in the function automatically?


    David Bishop had made a fixed point proposal. He modeled an
    unsigned fixed point number as foolows:
    variable nmbr : ufixed (1 downto -3)"
    With the interpretation 2 position on the left (index 1 and 0 in array)
    of the point and three on the right of the point (index -1, -2 and -3).

    In his proposal he can manipulate different fixed point numbers.
    In his case it is a benefit that the index is given to the function and
    not 'normalized' losing the information where the point is. In the
    latter case additional information would be needed (e.g. a record
    structure?)

    If you write a function and the index is to be normalized you can write
    FUNCTION (a : IN bit_vector ...) IS
    CONSTANT ai : bit_vector(a'LENGTH-1 DOWNTO 0) := a;
    and use ai internally.

    > 5. Is there a better way to bit reverse a bus than "new_bus(7 downto
    > 0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
    > hands cramps for large busses.


    Yes, create only once a function (you see I also used the index alignment
    here)

    FUNCTION bitr (i : std_logic_vector) RETURN std_logic_vector IS
    CONSTANT ii : std_logic_vector(i'LENGTH-1 DOWNTO 0) := i;
    VARIABLE o : std_logic_vector(i'LENGTH-1 DOWNTO 0);
    BEGIN
    FOR j IN 0 TO ii'LENGTH-1 LOOP
    o(j):=ii((ii'LENGTH-1)-j);
    END LOOP;
    RETURN o;
    END bitr;

    > 6. What advantage is there in not allowing an port output to not be
    > used on the rhs of an assignment in a module, forcing the RTL authors
    > to create internal versions of such signals (e.g., "signal oData_v
    > std_logic_vector(3 downto 0);") and later doing an assignment such as
    > "oData <= oData_v;"? I have actually seen RTL code from VHDL
    > engineers who did not know Verilog come up with even more ludicrous
    > ways of solving this problem (routing an output back into a module as
    > an input for use on the RHS of assigments inside the module).


    Reading mode OUT internally is currently considered to be part of the
    VHDL standard.

    ..
    >
    > I have concluded that the people who came up with VHDL syntax were not
    > working with each other, not referring back to previous decisions they
    > made when making new ones, and/or took the concept of "strongly typed"
    > to a ludicrous extreme.
    > It is also my belief that if it weren't for the government mandate,
    > and the hordes of VHDL-only engineers these mandates created (VHDL
    > fanatics who refuse to learn a better HDL), VHDL would be dead.
    >


    I must agree the learning curve of VHDL is not easy.
    But if you can 'play' with the language you can do nice things.

    Egbert Molenkamp
     
    Egbert Molenkamp, Aug 18, 2003
    #1
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