Re: VHDLisms

Discussion in 'VHDL' started by Willem Oosthuizen, Aug 18, 2003.

  1. I fully agree with your sentiments.

    Would it not be great if VHDL used curly brackets instead of begin...end

    Maybe people should look at how C is structured. The designers of C new
    something about engineers and computer people who prefer less words.

    Also why doesn't VHDL support text-replacement macros, and conditional
    signal declarations?

    Why do some Synthesis tools generate ripple tree structure of things like
    bit adders and gates, if fully synchronous designs are intended?

    "William Wallace" <> wrote in message
    > 1. Is there a general rule I can use to know when I need to use the
    > word "is" and when I do not? Also, what good does making somebody
    > type these two characters do?
    > 2. Is there a general rule I can use to figure out when two words are
    > combined into one word (e.g., "elsif") versus being kept as two words
    > (e.g., "end if")?
    > 3. Is there a general rule I can use to figure out when I need to put
    > a semicolon (e.g., after the generic section and also the port section
    > in the component declaration) and when I do not (e.g., not after the
    > generic section but only after a port section of an instantiation)?
    > 4. Why if I pass a argument, say a std_logic_vector, to a function
    > that takes a std_logic_vector, do I need to use data_in(arg'low) in
    > the function as opposed to data_in(0). Why doesn't VHDL automatically
    > rejustify a function call, say, function(data(15 downto 8)) to
    > data_in(7 downto 0) in the function automatically?
    > 5. Is there a better way to bit reverse a bus than "new_bus(7 downto
    > 0) <= old_bus(0) & old_bus(1) & ... & old_bus (7);", which gives my
    > hands cramps for large busses.
    > 6. What advantage is there in not allowing an port output to not be
    > used on the rhs of an assignment in a module, forcing the RTL authors
    > to create internal versions of such signals (e.g., "signal oData_v
    > std_logic_vector(3 downto 0);") and later doing an assignment such as
    > "oData <= oData_v;"? I have actually seen RTL code from VHDL
    > engineers who did not know Verilog come up with even more ludicrous
    > ways of solving this problem (routing an output back into a module as
    > an input for use on the RHS of assigments inside the module).
    > I have concluded that the people who came up with VHDL syntax were not
    > working with each other, not referring back to previous decisions they
    > made when making new ones, and/or took the concept of "strongly typed"
    > to a ludicrous extreme.
    > It is also my belief that if it weren't for the government mandate,
    > and the hordes of VHDL-only engineers these mandates created (VHDL
    > fanatics who refuse to learn a better HDL), VHDL would be dead.
    > Any VHDL apologists care to explain?
    > Thanks
    Willem Oosthuizen, Aug 18, 2003
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