Re: Why does the placement of a statement mater in vhdl, I thought itwas a parallel language ?

Discussion in 'VHDL' started by Andy, Sep 18, 2008.

  1. Andy

    Andy Guest

    While the subject of sequential execution of statements inside a
    process has been well covered here, the concept of signal assignments
    and updates has not.

    There are two kinds of objects that can be assigned in a process: a
    variable or a signal. As mentioned earlier, variable assignments
    operate just like in C or any other sequential language.

    Signal assignments in processes are executed sequentially, but to
    avoid ambiguity in inter-process communication (separate processes can
    execute in any order), signal value updates are delayed until the
    process suspends (waits). There is one and only one update to a given
    signal when the process suspends, regardless of the number of
    assignments to it that were executed. If multiple assignments are
    executed to a signal between successive process suspensions, the last
    executed assignment determines the update value.

    Hope this helps,

    Andy
     
    Andy, Sep 18, 2008
    #1
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