Re: Why does the placement of a statement mater in vhdl, I thoughtit was a parallel language ?

Discussion in 'VHDL' started by backhus, Sep 18, 2008.

  1. backhus

    backhus Guest

    Hi Morten,
    There are parallel as well as sequential statements available in VHDL.
    Assignment has identical syntax, but you have use e.g. "WITH" instead of
    "CASE" and "WHEN" instead of "IF" outside of a process.

    Inside a process you can use only sequential statements. You may also
    use variables, which behave like variables in a programming language.
    Their values are updated immediately after an assignment.

    Signals behave different in a process. You have to keep the
    reader-driver model of signals in mind. While the process is running all
    actual values of a signal are taken from it's reader-value. The Driver
    value will be overwritten on each occuring assignment of that signal
    during a process. At the end of a process or when a wait-statement stops
    the process the driver-value will be forwarded to the reader of the signal.
    This behavior of Signals can be very handy. Assume you have a large
    (combinatoric) case construct with a lot of output signals that rarely
    change. Instead of putting the whole list of output signals in each case
    branch you can put a default value list in front of the case and only
    vallues that differ from the default into the case branches. e.g.:

    process (selector, out1) is
    begin
    out1 <= '0'
    out2 <= '0'
    out3 <= '0'
    case selector is
    when 1 => null;
    when 2 => out1 <= '1';
    when 3 => out2 <= 'out1';
    when 4 => null;
    when 5 => out3 <= 'Z';
    when 6 => null;
    when others => out3 <= '1';
    end process;

    Delta delays have nothing to do with this.
    Delta delays happen when processes have to run multiple times to
    evaluate the results of all changing signals, caused by a single signal
    event.
    Assume selector changes from 1 to 2. This causes the above process to
    execute once which increments the delta delay value and causes out1 to
    change. This change again triggers the above process and increments the
    delta delay value. Since there's no change of any signal in this second
    run the simulator comes to a halt after two delta delays and looks for
    further events scheduled in the future to continue. (there may be more
    signals in your design!)


    Your process p_one_ff uses the signal rd_1_en in a similar way as
    described above.
    In p_constant_1 the assignment of rd_2_en at the end renders the
    if-construct useless. (the driver of rd_2_en will always be '1' at the
    end of the process, so rd_2_en never changes)

    Have a nice simulation
    Eilert


    Morten L. Haugen schrieb:
    > Why does the placement of a statement mater in vhdl, I thought it was a
    > parallel language )-:
    >
    >
    >
    > What vhdl mechanism occurs when the placement of a statement (before or
    > after an if statement) makes a complete different result in a clocked
    > process? First process below generates a flip-flop for rd_1_en, while the
    > second process below generates just a constant '1' for rd_2_en.
    >
    > Seems to be valid construction, checked with modelsim, synplify, Xilinx XST.
    >
    >
    >
    > I guess its delta delays defining what happens, any body who understand this
    > in detail?
    >
    > Same result in all tools?
    >
    >
    >
    > p_one_ff : process(clk)
    >
    > begin
    >
    > if rising_edge(clk) then
    >
    > rd_1_en <= '1'; -- statement in question !!!!!!!!
    >
    > if (sel_low = '1') then
    >
    > rd_1_en <= '0';
    >
    > end if;
    >
    > end if;
    >
    > end process p_one_ff;
    >
    >
    >
    > p_constant_1 : process(clk)
    >
    > begin
    >
    > if rising_edge(clk) then
    >
    > if (sel_low = '1') then
    >
    > rd_2_en <= '0';
    >
    > end if;
    >
    > rd_2_en <= '1'; -- statement in question !!!!!!!!
    >
    > end if;
    >
    > end process p_constant_1;
    >
    >
    >
    > Morten L. Haugen,
    >
    > GE Vingmed Ultrasound, Norway
    >
    >
    >
    >
     
    backhus, Sep 18, 2008
    #1
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