Re: Why doesn't this situation generate a latch?

Discussion in 'VHDL' started by Andy, Mar 18, 2010.

  1. Andy

    Andy Guest

    Andy

    "ever possible"? Yes. That's one reason why I prefer async resets for
    device initialization (but not for simply setting a counter back to
    zero during its normal course of operation, etc.)

    Andy
    Andy, Mar 18, 2010
    #1
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  2. On Mar 18, 8:00 am, Andy <> wrote:
    > Andy
    >
    > "ever possible"? Yes.  That's one reason why I prefer async resets for
    > device initialization (but not for simply setting a counter back to
    > zero during its normal course of operation, etc.)
    >
    > Andy


    fpgabuilder,

    From Sun code documents of OpenSparc CPU T2, there are 6 types of
    reset signals, a situation much more complexer than we think.

    Weng
    Weng Tianxiang, Mar 18, 2010
    #2
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  3. Andy

    rickman Guest

    On Mar 18, 11:41 am, Weng Tianxiang <> wrote:
    > On Mar 18, 8:00 am, Andy <> wrote:
    >
    > > Andy

    >
    > > "ever possible"? Yes.  That's one reason why I prefer async resets for
    > > device initialization (but not for simply setting a counter back to
    > > zero during its normal course of operation, etc.)

    >
    > > Andy

    >
    > fpgabuilder,
    >
    > From Sun code documents of OpenSparc CPU T2, there are 6 types of
    > reset signals, a situation much more complexer than we think.
    >
    > Weng


    Ok, go ahead and tease us! Or are you going to share with us what the
    six types are?

    Rick
    rickman, Mar 19, 2010
    #3
  4. Andy

    fpgabuilder Guest

    On Mar 19, 6:32 am, rickman <> wrote:
    > On Mar 18, 11:41 am, Weng Tianxiang <> wrote:
    >
    >
    >
    > > On Mar 18, 8:00 am, Andy <> wrote:

    >
    > > > Andy

    >
    > > > "ever possible"? Yes.  That's one reason why I prefer async resets for
    > > > device initialization (but not for simply setting a counter back to
    > > > zero during its normal course of operation, etc.)

    >
    > > > Andy

    >
    > > fpgabuilder,

    >
    > > From Sun code documents of OpenSparc CPU T2, there are 6 types of
    > > reset signals, a situation much more complexer than we think.

    >
    > > Weng

    >
    > Ok, go ahead and tease us!  Or are you going to share with us what the
    > six types are?
    >
    > Rick


    Yeah! What are those?
    fpgabuilder, Mar 19, 2010
    #4
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