Re: Xilinx VHDL coding styles,lookin for a tutorial

Discussion in 'VHDL' started by Mike Treseler, Dec 2, 2008.

  1. blisca wrote:

    > I am lookin for information about good coding style


    I use the same clocked process template for
    all of my synthesis code, for all designs
    and for all devices. Examples here:

    http://mysite.verizon.net/miketreseler/

    -- Mike Treseler
    Mike Treseler, Dec 2, 2008
    #1
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