Re: [XST 8.2.3] DSP48 inference multiply/add

Discussion in 'VHDL' started by Jonathan Bromley, Jan 4, 2007.

  1. On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
    <> wrote:

    [Also posted to comp.lang.vhdl]

    >ok, your right, now i know why it works on this code and not mine, in
    >the template i used the following libraries:
    >
    >LIBRARY ieee;
    >USE ieee.std_logic_1164.ALL;
    >use ieee.std_logic_arith.all;
    >use ieee.std_logic_signed.all;
    >
    >and in mine i used
    >
    >library IEEE;
    >use IEEE.STD_LOGIC_1164.ALL;
    >use IEEE.STD_LOGIC_ARITH.ALL;
    >use IEEE.STD_LOGIC_UNSIGNED.ALL;


    And that is PRECISELY why I keep banging on about why
    STD_LOGIC_(UN)SIGNED is such a very, very bad thing.

    If you had used only STD_LOGIC_ARITH or (better)
    NUMERIC_STD, then you would have been forced into
    declaring the objects as SIGNED or UNSIGNED, and you
    would know what you were doing. Having an arbitrary
    numeric representation imposed on std_logic_vector
    by a use clause is IMO certifiably insane.

    Thanks for providing more ammunition for my rant :)
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jan 4, 2007
    #1
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  2. Jonathan Bromley wrote:
    > On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
    > <> wrote:
    >
    > [Also posted to comp.lang.vhdl]
    >
    >> ok, your right, now i know why it works on this code and not mine, in
    >> the template i used the following libraries:
    >>
    >> LIBRARY ieee;
    >> USE ieee.std_logic_1164.ALL;
    >> use ieee.std_logic_arith.all;
    >> use ieee.std_logic_signed.all;
    >>
    >> and in mine i used
    >>
    >> library IEEE;
    >> use IEEE.STD_LOGIC_1164.ALL;
    >> use IEEE.STD_LOGIC_ARITH.ALL;
    >> use IEEE.STD_LOGIC_UNSIGNED.ALL;

    >
    > And that is PRECISELY why I keep banging on about why
    > STD_LOGIC_(UN)SIGNED is such a very, very bad thing.
    >
    > If you had used only STD_LOGIC_ARITH or (better)
    > NUMERIC_STD, then you would have been forced into
    > declaring the objects as SIGNED or UNSIGNED, and you
    > would know what you were doing. Having an arbitrary
    > numeric representation imposed on std_logic_vector
    > by a use clause is IMO certifiably insane.
    >
    > Thanks for providing more ammunition for my rant :)


    These newsgroups provide plenty
    of this sort of ammunition.
    The source, it seems to me,
    is the training examples and
    editor templates from brand X and brand S.

    The result is that most designers of
    VHDL synthesis code are convinced that
    using signed and unsigned types is a waste of time,
    and that only "purists" think otherwise.

    This state of affairs is only a problem
    for me when I use or supply entities to
    other designers. My workaround in this case
    is to declare [un]signed variables for use
    in my entity and implicit type conversion
    for port input and output assignments
    from the omnipresent std_logic_vector type.

    -- Mike Treseler
    Mike Treseler, Jan 5, 2007
    #2
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  3. On Fri, 05 Jan 2007 12:22:29 -0800, Mike Treseler
    <> wrote:

    >Jonathan Bromley wrote:
    >> On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
    >> <> wrote:
    >>
    >> [Also posted to comp.lang.vhdl]
    >>
    >>> ok, your right, now i know why it works on this code and not mine, in
    >>> the template i used the following libraries:
    >>>
    >>> LIBRARY ieee;
    >>> USE ieee.std_logic_1164.ALL;
    >>> use ieee.std_logic_arith.all;
    >>> use ieee.std_logic_signed.all;


    >> Thanks for providing more ammunition for my rant :)

    >
    >These newsgroups provide plenty
    >of this sort of ammunition.
    >The source, it seems to me,
    >is the training examples and
    >editor templates from brand X and brand S.


    Indeed. Furthermore, at least half the time, having included the
    std_logic_arith type libraries, the code doesn't ever use them!

    It is normal practice for me to comment out these "use" clauses;
    normally the code just compiles without them, and I have one less thing
    to worry about. (In the rare examples that actually use them, it's not
    usually difficult to make them numeric_std clean, though I don't always
    bother)

    - Brian
    Brian Drummond, Jan 6, 2007
    #3
  4. Jonathan Bromley

    yttrium Guest

    i have to admit at first i was not really convinced but by writing more
    and more DSP related VHDL where i need signed/unsigned values i am
    learning a lot of the inefficiency of certain libraries and packages ...

    Mike Treseler wrote:
    > Jonathan Bromley wrote:
    >> On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete"
    >> <> wrote:
    >>
    >> [Also posted to comp.lang.vhdl]
    >>
    >>> ok, your right, now i know why it works on this code and not mine, in
    >>> the template i used the following libraries:
    >>>
    >>> LIBRARY ieee;
    >>> USE ieee.std_logic_1164.ALL;
    >>> use ieee.std_logic_arith.all;
    >>> use ieee.std_logic_signed.all;
    >>>
    >>> and in mine i used
    >>>
    >>> library IEEE;
    >>> use IEEE.STD_LOGIC_1164.ALL;
    >>> use IEEE.STD_LOGIC_ARITH.ALL;
    >>> use IEEE.STD_LOGIC_UNSIGNED.ALL;

    >> And that is PRECISELY why I keep banging on about why
    >> STD_LOGIC_(UN)SIGNED is such a very, very bad thing.
    >>
    >> If you had used only STD_LOGIC_ARITH or (better)
    >> NUMERIC_STD, then you would have been forced into
    >> declaring the objects as SIGNED or UNSIGNED, and you
    >> would know what you were doing. Having an arbitrary
    >> numeric representation imposed on std_logic_vector
    >> by a use clause is IMO certifiably insane.
    >>
    >> Thanks for providing more ammunition for my rant :)

    >
    > These newsgroups provide plenty
    > of this sort of ammunition.
    > The source, it seems to me,
    > is the training examples and
    > editor templates from brand X and brand S.
    >
    > The result is that most designers of
    > VHDL synthesis code are convinced that
    > using signed and unsigned types is a waste of time,
    > and that only "purists" think otherwise.
    >
    > This state of affairs is only a problem
    > for me when I use or supply entities to
    > other designers. My workaround in this case
    > is to declare [un]signed variables for use
    > in my entity and implicit type conversion
    > for port input and output assignments
    > from the omnipresent std_logic_vector type.
    >
    > -- Mike Treseler
    >
    yttrium, Jan 6, 2007
    #4
  5. Jonathan Bromley

    Ray Andraka Guest

    yttrium wrote:

    > i have to admit at first i was not really convinced but by writing more
    > and more DSP related VHDL where i need signed/unsigned values i am
    > learning a lot of the inefficiency of certain libraries and packages ...
    >



    By the same token, if you do a lot of DSP, you'll soon learn to
    appreciate the strong typing in VHDL as compared to verilog, and may
    even grow to despise the permissiveness (and ambiguity) of verilog.

    FWIW, I code my VHDL components with std_logic and std_logic_vector on
    the I/O in order to be consistent with existing libraries. I convert
    the signals to signed/unsigned inside the architecture as needed. Some
    of my components have a boolean generic, "is_signed" to specify the
    behavior as an option.
    Ray Andraka, Jan 8, 2007
    #5
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