read from a file

Discussion in 'VHDL' started by axr0284, Jul 31, 2009.

  1. axr0284

    axr0284 Guest

    Hi,
    I am getting an error from my simulator, Aldec Active HDL with the
    following code:
    <CODE>
    library ieee;
    use ieee.std_logic_1164.all;
    use std.textio.ALL;
    use ieee.std_logic_textio.all;
    ....
    ....
    ....
    signal current : STD_LOGIC_VECTOR(15 downto 0);
    signal voltage : STD_LOGIC_VECTOR(15 downto 0);
    file voltage_file_stimulus: TEXT open read_mode is
    "vhdl_voltage_data.dat";
    file current_file_stimulus: TEXT open read_mode is
    "vhdl_current_data.dat";
    begin
    ....
    ....
    ....
    process
    variable lineFromFile : line;
    variable v_current : STD_LOGIC_VECTOR(15 downto 0);
    variable v_voltage : STD_LOGIC_VECTOR(15 downto 0);
    begin
    reset <= '1';
    absolutethreshold <= x"01BF3A11";
    wait for 100 ns;
    reset <= '0';
    wait for 100 ns;

    while (NOT endfile(voltage_file_stimulus)) AND (NOT endfile
    (voltage_file_stimulus)) loop
    readline(voltage_file_stimulus, lineFromFile); -- Read 1 line
    read(lineFromFile,v_voltage);
    voltage <= v_voltage;

    readline(current_file_stimulus, lineFromFile); -- Read 1
    line
    read(lineFromFile,v_current);
    current <= v_current;

    wait for CLK_PERIOD;

    end loop;

    wait;
    end process;
    </CODE>

    The text files contains the following data set:
    560
    386F
    3087
    3326
    3E85
    AD5
    FBA
    9C4
    3D07
    325C

    I am getting these errors:
    # KERNEL: Time: 0 ps, Iteration: 2, Instance: /UUT/
    ray_event_classification_block/area_summer, Process: line__2260.
    # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '5'
    read, expected STD_ULOGIC literal.
    # EXECUTION:: Time: 200 ns, Iteration: 0, TOP instance, Process:
    line__67.
    # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '3'
    read, expected STD_ULOGIC literal.
    # EXECUTION:: Time: 200 ns, Iteration: 0, TOP instance, Process:
    line__67.
    # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '3'
    read, expected STD_ULOGIC literal.
    # EXECUTION:: Time: 210 ns, Iteration: 0, TOP instance, Process:
    line__67.
    # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '3'
    read, expected STD_ULOGIC literal.
    # EXECUTION:: Time: 210 ns, Iteration: 0, TOP instance, Process:
    line__67.
    # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '3'
    read, expected STD_ULOGIC literal.
    # EXECUTION:: Time: 220 ns, Iteration: 0, TOP instance, Process:
    line__67.
    # KERNEL: ERROR : TextIO internal error: Could not read type "STRING"
    from line.

    I would appreciate any help figuring this out. Thanks a lot,
    Amish
    axr0284, Jul 31, 2009
    #1
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  2. axr0284 wrote:

    > I am getting an error from my simulator, Aldec Active HDL with the
    > following code:
    > <CODE>

    ....
    > The text files contains the following data set:
    > 560
    > 386F
    > 3087
    > 3326
    > 3E85
    > AD5
    > FBA
    > 9C4
    > 3D07
    > 325C


    > I am getting these errors:


    > # EXECUTION:: ERROR : READ(STD_ULOGIC_VECTOR) Error: Character '5'
    > read, expected STD_ULOGIC literal.


    Textio is a pain.
    Try a constant array as demonstrated below.

    -- Mike Treseler

    _______________________________________________________________________
    library ieee;
    use ieee.std_logic_1164.all;
    package expect_pkg is
    constant vec_len_c : positive := 16;
    constant array_len_c : positive := 10;
    subtype vec_t is std_logic_vector(vec_len_c-1 downto 0);
    type array_t is array (0 to array_len_c-1) of vec_t;
    constant expect_c : array_t
    := (
    x"0560",
    x"386F",
    x"3087",
    x"3326",
    x"3E85",
    x"0AD5",
    x"0FBA",
    x"09C4",
    x"3D07",
    x"325C"
    );
    end package expect_pkg;
    -------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use work.expect_pkg.all;
    entity test_expect is
    end entity test_expect;
    architecture sim of test_expect is

    begin -- architecture sim

    p : process is
    begin
    assert expect_c(0) = x"0560";
    assert expect_c(9) = x"325C";
    report "Test complete. Expect no assertions above";
    wait;
    end process p;
    end architecture sim;


    --58 Fri Jul 31 /evtfs/home/tres/vhdl/play> vcom expect_pkg.vhd
    ---- Loading package standard
    ---- Loading package std_logic_1164
    ---- Compiling package expect_pkg
    ---- Loading package expect_pkg
    ---- Compiling entity test_expect
    ---- Compiling architecture sim of test_expect

    --59 Fri Jul 31 /evtfs/home/tres/vhdl/play> vsim -c test_expect
    --# vsim -c test_expect
    --# Loading /flip/usr1/modeltech/linux/../std.standard
    --# Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body)
    --# Loading work.expect_pkg
    --# Loading work.test_expect(sim)
    --VSIM 1> run
    --# ** Note: Test complete. Expect no assertions above
    --# Time: 0 ns Iteration: 0 Instance: /test_expect
    --VSIM 2>
    Mike Treseler, Jul 31, 2009
    #2
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  3. axr0284

    JimLewis Guest

    Amish,
    The error message is telling you that when you read std_logic_vector,
    it is expecting std_ulogic (std_logic) character values. Meaning
    bits of 1 and 0.

    In the std_logic_textio package that you referenced, there is an
    hread. You will want to try this.

    You will still have problems though. Since v_current and v_voltage
    are 16 bits, you will need to read 4 hexadecimal characters. So
    you will need to revise your file to have leading 0 where the
    character is 0.

    Cheers,
    Jim Lewis
    SynthWorks VHDL Training
    JimLewis, Jul 31, 2009
    #3
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