read hex file in VHDL using modelsim

Discussion in 'VHDL' started by Carson, Sep 3, 2005.

  1. Carson

    Carson Guest

    Hi ,

    I have a difficulty when I wants to read out hex format file in
    vhdl. what's the best way to do? (I am using modelsim). An example of
    my file is like this:

    AB412266
    BB329EF1
    133F

    Thanks!

    Carson
     
    Carson, Sep 3, 2005
    #1
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  2. Carson

    Ajeetha Guest

    Hi,
    Try using hread procedure (I believe it is part of
    ieee.std_logic_textio for slv data type). Refer to VHDL FAQ for basic
    example:
    http://www.vhdl.org/comp.lang.vhdl/

    4.2.12 How to Use Package Textio for Accessing Text Files

    HTH
    Ajeetha
    www.noveldv.com
     
    Ajeetha, Sep 3, 2005
    #2
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  3. Carson

    Guest


    > (I am using modelsim)

    In my opinion, that should not make a difference. ModelSim is only a
    simulator and compiler software. The language constructs you use are
    native to VHDL and will work on any simulator. Probably the only thing
    you should check is which VHDL version your ModelSim supports.
     
    , Sep 4, 2005
    #3
  4. Carson

    Beanut Guest

    I would expect simulators to handle data based on their own formats
    which could make each one different. I know that modelsim will read
    std_logic from a binary file if it is coded x"03" for a '1' and x"02"
    for a '0'. If that same file were read as a bit_vector the x"03"
    would be x"03", not '1'. I doubt that x"03" is a standard for all
    simulators trying to ready a binary file of stand logic data. Correct
    me if this assumption is wrong please.
     
    Beanut, Sep 6, 2005
    #4
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