read input file in vhdl !

Discussion in 'VHDL' started by charko, May 19, 2010.

  1. charko

    charko

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    Hi! I am new for the vhdl and i want to know how i can test reading input file.
    I write this code to read an input file but i don't have idea to write a test bench for the simulation.
    Thank you for your help!
    Charko

    NB: Sorry for my bad english!

    You can find following the code vhdl for reading input file :
    library std;
    use std.textio.all;

    entity lecture is end;

    architecture arch of lecture is
    begin
    read_imput_file : process
    variable inline: line;
    variable character_variable:character;
    variable end_of_line: boolean ;
    file myfile: text is "data.txt";
    begin
    while not endfile(myfile ) loop -- tant qu'on a pas la fin du fichier on fait une boucle
    readline(myfile,inline); -- on lit tout le fichier
    read(inline,character_variable,end_of_line);
    --end_of_line is EOLN Boolean flag
    while end_of_line loop -- tant qu'on atteint la fin du fichier
    read(inline,character_variable,end_of_line);
    end loop;
    end loop;
    wait; -- ne rien faire lorsque c'est fini
    end process read_imput_file;
    end arch;
     
    Last edited: May 19, 2010
    charko, May 19, 2010
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  2. charko

    charko

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    hi everybody!

    Please can you help, i want to know how i can write a vhdl code for binary file.
    Thank you very munch!

    Charko
     
    charko, May 19, 2010
    #2
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