Reading and "storing" 32 bits values

C

Clemens

Hi

I wanna find a proper solution for the following task.

I have got an coprocessor which processes 128 bit values at once. But my
interface to the processor has
only got a 32 bit interface. Therefore I have a statemachine which reads me
in the 32 bits values one after another, "stores" them in a 128 bits
register (after 4 read states my 128bit Register is filled with the values)
and then I store this 128 value in my register file of my coprocessor.

Currently I have implemented this in the following way:

when IDLE => if new_Value = '1' then
next_state <= LD;
else
next_state <= IDLE;
end if;

when LD => case current_count is
when 3 => ld <= "11";
when 2 => ld <= "10";
when 1 => ld <= "01";
when 0 => ld <= "00";
end case;
next_count <= current_count-1;
next_state <= WAIT1;

when WAIT1 => if (current_count > 0) then
nextstate <= IDLE;
else nextstate <= STORE;

when STORE => data_in_memory <= reg1;
wr_addr <= addr;
wr <= '1';

sync process:
elsif clk'event and clk = '1' then
case ld is
when "00" => reg1(127 downto 96) <= inp;
when "01" => reg1(95 downto 64) <= inp;
when "10" => reg1(63 downto 32) <= inp;
when "11" => reg1(31 downto 0) <= inp;
end case;

I have modified the code a little bit so that it is easier readable. It
works fine, but I wonder if there is a nicer, more professional way to solve
this task. Because the way I do it I need an 128 bit latch, to store my
value before I write it to the memory.

Thanks for every useful tip
 
M

Mike Treseler

Clemens said:
I have modified the code a little bit so that it is easier readable. It
works fine, but I wonder if there is a nicer, more professional way to solve
this task. Because the way I do it I need an 128 bit latch, to store my
value before I write it to the memory.

It's readable, it's synchronous, it fits and it works.
If the fpga and coprocessor use the same clock,
I don't see much more design work to do.
The 128 bits of register are essential.

The "professional" aspect includes completing
verification and documentation:

Verify Fmax margin in the static timing report.
Upgrade your vhdl testbench to pass/fail.
Check the test coverage and add some corner cases to your testbench.
Cut the operation description from your
posting here and paste it as a comment into your source code.
Check all the vhdl and script sources into an RCS directory
or CVS server to control changes and versions.

-- Mike Treseler
 

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