reading file inside procedure

Discussion in 'VHDL' started by Olaf Petzold, Nov 19, 2005.

  1. Olaf Petzold

    Olaf Petzold Guest

    Hello,

    the follwing code has worked inside a process; any more inside a
    procedure. What's gone wrong here?

    architecture ...
    constant TIMESTAMP_SZ : positive := 10;
    constant SAMPLE_SZ : positive := 16;
    constant NUM_SAMPLES : positive := 1536;

    type sample_t is record
    time : std_logic_vector(TIMESTAMP_SZ-1 downto 0);
    data : std_logic_vector(SAMPLE_SZ-1 downto 0);
    end record;
    type sample_vec_t is array (natural range <>) of sample_t;

    signal tv_samples : sample_vec_t(NUM_SAMPLES-1 downto 0);

    ....
    tb: process is
    ...
    procedure load_sample_tv (constant name : in string) is

    function str2slv(vec : string) return std_logic_vector is
    variable temp : std_logic_vector(vec'range)
    := (others => 'X');
    begin
    for i in vec'range loop
    if (vec(i) = '1') then
    temp(i) := '1';
    elsif (vec(i) = '0') then
    temp(i) := '0';
    end if;
    end loop;
    return temp;
    end function;

    file m_fd : text open read_mode is name;
    variable L : line;
    variable m_memblk : std_logic_vector(25 downto 0);
    variable m_str : string(26 downto 1);
    variable i : integer := 0;

    begin
    m_memblk := (others => 'X');

    while not endfile(m_fd) loop
    readline(m_fd, L);
    read(L, m_str);
    deallocate(L);
    m_memblk := str2slv(m_str);
    tv_samples(i).time <= m_memblk(25 downto 16);
    tv_samples(i).data <= m_memblk(15 downto 0);
    i := i + 1;
    write(output,
    image(tv_samples(i).time&tv_samples(i).data));
    end loop;

    end procedure load_sample_tv;

    ...

    While I've got inside the loop for m_memblock my bit pattern, the
    output displayed for the statements here got "UUUUU.......". I can't
    see my fault.

    Thanks
    Olaf
     
    Olaf Petzold, Nov 19, 2005
    #1
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  2. Olaf Petzold

    Olaf Petzold Guest

    Stop, all things are working if I wait for a clock cycle, which I
    didn't before. Using wait statements for my TB design needs some kind
    of care by me (normally I used to sens. list).

    Thanks
    Olaf
     
    Olaf Petzold, Nov 19, 2005
    #2
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  3. Olaf Petzold wrote:
    > Stop, all things are working if I wait for a clock cycle, which I didn't
    > before. Using wait statements for my TB design needs some kind of care
    > by me (normally I used to sens. list).


    That's it.
    Update signals,
    wait for a rising edge,
    repeat.

    You can write straight line code
    or collect repeated statements
    into procedures.

    -- Mike Treseler
     
    Mike Treseler, Nov 19, 2005
    #3
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