Reading from FPGA Issue

I

Isaac

Hi Guys

I am trying to read 36 signal one by one from FPGA using different
addresses and these signal are of 3 bits length. My address bus is
bidirectional (32 bit length)and it's on tristate while not performing
read operations.
I am using PCI API fucntion to perform open , read and write
operations as it is PCI FPGA reconfigurable board having XCV600
device. The values are being read by using SRAM in the board and I am
using addresses which are properly mapped to PCI bus and Onboard
Memory. Now the problem is that I delebrately make a loop to read the
sequence of signal again and again in order to make sure I am reading
the correct output every time. But the thing is that in different
iteration the values of different signal are not the same. it means
that the signal which is being read is changing all the time. But
according to simulated desing this is not the case , I must have been
reading the correct output everytime .
Is there is any design constraint ? My desing has internal clock as
well is this is affecting the signal. But in simulation this is not
the case .


Also one thing more does the VHDL coding style effect the read from
FPGA or not. Because in my other desing I have state machine and
number of different states in the Process (desing is synchronous) and
I am using CASE statement to move from one state to another. When I
download this into the chip and when I perform read operation after
writing data into the chip I am getting nothing from FPG.
If any one can tell me how to stabilize particular signal so that it
could to read oout from FPGA.

Cheers
Help would be appreciated.

Rgds

Isaac
 
M

Mario Trams

Isaac wrote:

Hi Isaac,
I am trying to read 36 signal one by one from FPGA using different
addresses and these signal are of 3 bits length. My address bus is
bidirectional (32 bit length)and it's on tristate while not performing
read operations.
I am using PCI API fucntion to perform open , read and write
operations as it is PCI FPGA reconfigurable board having XCV600
device. The values are being read by using SRAM in the board and I am
using addresses which are properly mapped to PCI bus and Onboard
Memory. Now the problem is that I delebrately make a loop to read the
sequence of signal again and again in order to make sure I am reading
the correct output every time. But the thing is that in different
iteration the values of different signal are not the same. it means
that the signal which is being read is changing all the time. But
according to simulated desing this is not the case , I must have been
reading the correct output everytime .
Is there is any design constraint ? My desing has internal clock as
well is this is affecting the signal. But in simulation this is not
the case .
Click to expand...

Your problem is almost impossible to be solved from remote.
You say that it is working well in simulation. Do you mean
functional simulation (i.e. pure VHDL code) or back-annotated
simulation (i.e. simulation of the synthesized design including
estimated delays etc.)?

Are you also sure that you meet all timing parameters when
accessing the RAM?
Also one thing more does the VHDL coding style effect the read from
FPGA or not. Because in my other desing I have state machine and
number of different states in the Process (desing is synchronous) and
I am using CASE statement to move from one state to another. When I
download this into the chip and when I perform read operation after
writing data into the chip I am getting nothing from FPG.
If any one can tell me how to stabilize particular signal so that it
could to read oout from FPGA.
Click to expand...

Absolutely! VHDL coding style might have heavy impact on the result.
To give an example effect I once encountered with Synopsys:
When you have a clocked process with asynchronous reset and a couple
of registers inside, and you forget to include one signal in the
reset clause, then Synopsys created a register where the output
is feed back and is ORed at the input. As a result, once the
register turns to '1', it can never turn to '0' again.
But in functional simulation you do not see that effect (exept from
the fact that the register is not initialized during reset).

That's another reason why it is important to simulate the
synthesized design.

Regards,
Mario
 
C

Charles M. Elias

Hi Guys

I am trying to read 36 signal one by one from FPGA using different
addresses and these signal are of 3 bits length. My address bus is
bidirectional (32 bit length)and it's on tristate while not performing
read operations.
I am using PCI API fucntion to perform open , read and write
operations as it is PCI FPGA reconfigurable board having XCV600
device. The values are being read by using SRAM in the board and I am
using addresses which are properly mapped to PCI bus and Onboard
Memory. Now the problem is that I delebrately make a loop to read the
sequence of signal again and again in order to make sure I am reading
the correct output every time. But the thing is that in different
iteration the values of different signal are not the same. it means
that the signal which is being read is changing all the time. But
according to simulated desing this is not the case , I must have been
reading the correct output everytime .
Is there is any design constraint ? My desing has internal clock as
well is this is affecting the signal. But in simulation this is not
the case .


Also one thing more does the VHDL coding style effect the read from
FPGA or not. Because in my other desing I have state machine and
number of different states in the Process (desing is synchronous) and
I am using CASE statement to move from one state to another. When I
download this into the chip and when I perform read operation after
writing data into the chip I am getting nothing from FPG.
If any one can tell me how to stabilize particular signal so that it
could to read oout from FPGA.

Cheers
Help would be appreciated.

Rgds

Isaac
Click to expand...


Without seeing your code it is not possible to make an exact diagnosis
(maybe I couldn't even if I did see it), but I do have suggestions.
Any signal that is an input to the FPGA synchronous logic should be
internally synchronized with the logic's clock using 2 d flip-flops.
The bus data need not be synchronized in this manner if the transfer
logic (handshake) is synchronized. The read operation should have
some sort of handshake to ensure that the output data is stable before
it is read and that the FPGA logic "knows" when new data is requested.
Does PCI protocol involve a handshake? If so, have you implemented
it on the FPGA side?

A typical handshake would be: The reader asserts data_request; the
FPGA logic puts the data on the bus and asserts data_ready. The
reader sees data_ready, reads the data, and unasserts data_request
(this lets the FPGA logic know that the data has been read and it
unasserts data_ready and). There are a number of variations on this,
but without some sort of handshake it is quite likely that there will
be missed data, multiple reads of the same data, etc.

Charles
 
I

Isaac

(e-mail address removed) (Isaac) wrote in message



Without seeing your code it is not possible to make an exact diagnosis
(maybe I couldn't even if I did see it), but I do have suggestions.
Any signal that is an input to the FPGA synchronous logic should be
internally synchronized with the logic's clock using 2 d flip-flops.
The bus data need not be synchronized in this manner if the transfer
logic (handshake) is synchronized. The read operation should have
some sort of handshake to ensure that the output data is stable before
it is read and that the FPGA logic "knows" when new data is requested.
Does PCI protocol involve a handshake? If so, have you implemented
it on the FPGA side?

A typical handshake would be: The reader asserts data_request; the
FPGA logic puts the data on the bus and asserts data_ready. The
reader sees data_ready, reads the data, and unasserts data_request
(this lets the FPGA logic know that the data has been read and it
unasserts data_ready and). There are a number of variations on this,
but without some sort of handshake it is quite likely that there will
be missed data, multiple reads of the same data, etc.

Charles
--------------------

Without seeing your code it is not possible to make an exact diagnosis
(maybe I couldn't even if I did see it), but I do have suggestions.
Any signal that is an input to the FPGA synchronous logic should be
internally synchronized with the logic's clock using 2 d flip-flops.
The bus data need not be synchronized in this manner if the transfer
logic (handshake) is synchronized. The read operation should have
some sort of handshake to ensure that the output data is stable before
it is read and that the FPGA logic "knows" when new data is requested.
Does PCI protocol involve a handshake? If so, have you implemented
it on the FPGA side?

A typical handshake would be: The reader asserts data_request; the
FPGA logic puts the data on the bus and asserts data_ready. The
reader sees data_ready, reads the data, and unasserts data_request
(this lets the FPGA logic know that the data has been read and it
unasserts data_ready and). There are a number of variations on this,
but without some sort of handshake it is quite likely that there will
be missed data, multiple reads of the same data, etc.

Charles
Click to expand...
-------------------------------------------------------------------
Here is the Case Statement which I am using, in this you will see
different signal which I am using in differnt process which I haven't
included .


process1: process (CLK_2X)
begin
if RISING_EDGE(CLK_2X) then
state <= next_state;
else
Null;
end if;
end process process1;
process2 : process
(state,LOCKED,CLK_2X,SR_ADDR_IO,SR_DATA_IO,SR_IRD,SR_IWR,SR_IVCS_V3)
begin
case state is
when s1 =>
paritycheck <= '0';
k <= 0;
next_state <= s2;
when s2 =>
if LOCKED = '1' then
-- LED_V3 <= LED_V3_int;
STAT_V3 <= STAT_V3_int;
-- Inputs
-- SR_ADDR_IO_int <= SR_ADDR_IO;
-- SR_DATA_IO_int <= SR_DATA_IO;
-- SR_IRD_int <= SR_IRD;
-- SR_IWR_int <= SR_IWR;
SR_IVCS_V3_int <= SR_IVCS_V3;
next_state <= s3; else
Null;
end if;

when s3 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000000" then
channelbit1 <= SR_DATA_IO(2 downto 0) ;
next_state <= s32;
else
next_state <= s3;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s32 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000001" then
channelbit2 <= SR_DATA_IO(2 downto 0) ;
next_state <= s33;
else
next_state <= s32;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s33 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000010" then
channelbit3 <= SR_DATA_IO(2 downto 0) ;
next_state <= s34;
else
next_state <= s33;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s34 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000011" then
channelbit4 <= SR_DATA_IO(2 downto 0) ;
next_state <= s35;
else
next_state <= s34;
end if ;
else
Null;
end if ;
else
Null;
end if;

when s35 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO <= "000100" then
channelbit5 <= SR_DATA_IO(2 downto 0) ;
next_state <= s36;
else
next_state <= s35;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s36 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000101" then
channelbit6 <= SR_DATA_IO(2 downto 0) ;
next_state <= s37;
else
next_state <= s36;
end if ;
else
Null;
end if ;
else
Null;
end if;

when s37 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000110" then
channelbit7 <= SR_DATA_IO(2 downto 0) ;
next_state <= s38;
else
next_state <= s37;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s38 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "000111" then
channelbit8 <= SR_DATA_IO(2 downto 0) ;
next_state <= s39;
else
next_state <= s38;
end if ;
else
Null;
end if ;
else
Null;
end if;

when s39 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "001000" then
channelbit9 <= SR_DATA_IO(2 downto 0) ;
next_state <= s310;
else
next_state <= s39;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s310 =>

if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "001001" then
channelbit10 <= SR_DATA_IO(2 downto 0) ;
next_state <= s311;
else
next_state <= s310;
end if ;
else
Null;
end if ;
else
Null;
end if;
when s311 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "001010" then
channelbit11 <= SR_DATA_IO(2 downto 0) ;
next_state <= s312;
else
next_state <= s311;
end if ;
else
Null;
end if ;
else
Null;
end if ;
when s312 =>
if SR_IVCS_V3 = '0' then
SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if SR_IWR = '0' then
if SR_ADDR_IO = "001011" then
channelbit12 <= SR_DATA_IO(2 downto 0) ;
LED_V3(2 downto 0) <= channelbit11;
next_state <= s4;
else
next_state <= s312;
end if ;
else
Null;
end if ;
else
Null;
end if;

when s4 =>
k <= k + 1;
next_state <= s5;
when s5 =>
if remainder = 0 then
k <= 0;
next_state <= s6 ;
paritycheck <= '1';
else
next_state <= s4 ;
k<= k+1;
end if ;
when s6 =>
if SR_IVCS_V3 = '0' then
if SR_IRD = '0' then
-- if remainder = 0 then
if SR_ADDR_IO = "001100" then
SR_DATA_IO (11 downto 0)<= eb_hat_bits (0 to 11);
SR_DATA_IO (31 downto 12) <= "00000000000000000000";
elsif SR_ADDR_IO = "001101" then
next_state <= s1;
end if;
-- end if;
else
Null;
end if;
else
Null;
end if ;
when others =>
Null;
end case;
end process process2;
 
I

Isaac

--------------------
Here is the Case Statement which I am using, in this you will see
 

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