"Real" Simulations?

Discussion in 'VHDL' started by Jay Davis, Nov 21, 2003.

  1. Jay Davis

    Jay Davis Guest

    I'm currently using Xilinx Webpack and modelsim to develop a project
    (yes, it's a class assignment). The problem is, I'm not allowed to take
    the FPGA board out of the lab, and I'd like to work on some of the
    project at home. I was wondering if there exists any sort of software
    that would be able to drive the parallel port of a PC with the outputs
    of a VHDL simulation? In other words, would it be possible to use a
    simulation to drive some logic values onto the parallel port which I
    could then pretend were the outputs of my FPGA chip (and then use those
    outputs to test my VHDL code with the rest of my circuit)? I realize
    that I would have some limitations on speed, but it ought to be
    theoretically possible (or maybe not, that's why I'm asking!).

    Thanks for any pointers!

    Jay
     
    Jay Davis, Nov 21, 2003
    #1
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  2. Jay Davis wrote:

    > I'm currently using Xilinx Webpack and modelsim to develop a project
    > (yes, it's a class assignment). The problem is, I'm not allowed to take
    > the FPGA board out of the lab, and I'd like to work on some of the
    > project at home. I was wondering if there exists any sort of software
    > that would be able to drive the parallel port of a PC with the outputs
    > of a VHDL simulation?


    Consider watching those outputs as modelsim waves
    and then close the loop and have your testbench
    verify the expected outputs.

    -- Mike Treseler
     
    Mike Treseler, Nov 21, 2003
    #2
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  3. Jay Davis

    Jay Davis Guest

    Mike Treseler wrote:

    > Consider watching those outputs as modelsim waves
    > and then close the loop and have your testbench
    > verify the expected outputs.


    I'm sorry, I don't understand what you mean by "close the loop". I
    don't want to write code to drive a parallel port, I want a program that
    can drive a parallel port with the output waveform of a modelsim run.
    In this way, I would not need physical access to a FPGA chip to test my
    design with my other hardware - I could use the PC instead.

    --
    Jay
     
    Jay Davis, Nov 21, 2003
    #3
  4. "Jay Davis" <> wrote in message
    news:vXivb.429855$...

    > > Consider watching those outputs as modelsim waves
    > > and then close the loop and have your testbench
    > > verify the expected outputs.

    >
    > I'm sorry, I don't understand what you mean by "close the loop". I
    > don't want to write code to drive a parallel port, I want a program that
    > can drive a parallel port with the output waveform of a modelsim run.
    > In this way, I would not need physical access to a FPGA chip to test my
    > design with my other hardware - I could use the PC instead.


    Mike is pushing you towards a professional's view of
    simulation:

    1) Use the simulator as a debug tool, to help you get the
    design basically working. At this stage you are likely
    to make heavy use of the waveform view, code tracing and
    breakpoints, and other debug features of the simulator
    that help you probe around inside your code.
    2) Once your design is showing real signs of life, you can
    start to use the simulator as a *verification* tool. To
    do this properly, you need to get the testbench to predict
    what the outputs should be for any given stimulus.
    Then the testbench itself can compare the expected output
    with the simulated design's output, and report any
    discrepancies - probably in the form of text messages
    from assert statements.

    Whether you are ready for this depends on how confident you
    are in writing VHDL for testbenches - a very different art
    from writing designs.

    To go back to your original question: No, I don't know of
    any simulation tools that allow you to use real PC peripherals
    to mimic I/O in your simulated system. In any case, it would
    be desperately limiting to have only the PC's I/O facilities -
    the great thing about simulation is that you are limited only
    by your imagination. However, a common approach to this kind
    of problem is to mock-up your external system (a few buttons
    and lights, in your case?) using Tcl/Tk, Visual Basic or some
    similar GUI-creation system. Then you need to find some way
    to get this system mock-up to talk to your VHDL simulator.
    If you have the full (SE) version of ModelSim, that's rather
    easy because you can write Tcl/Tk GUIs within ModelSim itself;
    otherwise, it's a bit more tricky because you need to have
    two independent programs talking to one another. Either
    way, it's sure to be harder work than writing a classic
    self-checking VHDL testbench as Mike suggested.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Nov 21, 2003
    #4
  5. Jay Davis <> wrote in message news:<77hvb.423205$>...
    > I'm currently using Xilinx Webpack and modelsim to develop a project
    > (yes, it's a class assignment). The problem is, I'm not allowed to take
    > the FPGA board out of the lab, and I'd like to work on some of the
    > project at home. I was wondering if there exists any sort of software
    > that would be able to drive the parallel port of a PC with the outputs
    > of a VHDL simulation? In other words, would it be possible to use a
    > simulation to drive some logic values onto the parallel port which I
    > could then pretend were the outputs of my FPGA chip (and then use those
    > outputs to test my VHDL code with the rest of my circuit)? I realize
    > that I would have some limitations on speed, but it ought to be
    > theoretically possible (or maybe not, that's why I'm asking!).
    >
    > Thanks for any pointers!
    >
    > Jay

    Jay,

    Make a VHDL model of the "rest of your circuit"--I'll call it
    device_b. Make a component of your FPGA device (device_a) and
    instantiate it in a testbench for device_b. Use the outputs of
    device_a (device_a is driven by the inputs you used to test it) as
    inputs to device_b. You "close the loop" by monitoring device_b's
    outputs and checking them for correctness either by inspection or by
    writing VHDL code to verify the outputs.

    The answer to your question about using the parallel port is: It
    depends. It is theoretically possible if you are not asking for too
    many signal outputs, but I don't know of any software that would do
    the job for you. Since your time is probably limited, the testbench
    solution is more practical, I think.

    Best regards,

    Charles
     
    Charles M. Elias, Nov 21, 2003
    #5
  6. Jay Davis

    Jay Davis Guest

    Charles M. Elias wrote:

    > Make a VHDL model of the "rest of your circuit"--I'll call it
    > device_b. Make a component of your FPGA device (device_a) and
    > instantiate it in a testbench for device_b. Use the outputs of
    > device_a (device_a is driven by the inputs you used to test it) as
    > inputs to device_b. You "close the loop" by monitoring device_b's
    > outputs and checking them for correctness either by inspection or by
    > writing VHDL code to verify the outputs.


    Ah, I understand now. This would work if the "rest of my circuit" was
    simple (just a few buttons and LEDs, as another poseter suggested), but
    what I'm doing is interfacing a (256x128) LCD, and modeling an LCD in
    VHDL isn't going to be practical. I have my code already generating the
    right sequence of commands to do what I want (judging by the testbench
    waveform output), but it's difficult to be sure that I have all the
    timing issues correctly sorted out when I only have physical access to
    the FPGA for three hours a week.

    > The answer to your question about using the parallel port is: It
    > depends. It is theoretically possible if you are not asking for too
    > many signal outputs, but I don't know of any software that would do
    > the job for you. Since your time is probably limited, the testbench
    > solution is more practical, I think.


    All right, that's what I figured. Sounds like I'll just do the best I
    can and petition for more lab time!

    Thanks,
    Jay
     
    Jay Davis, Nov 21, 2003
    #6
  7. On Fri, 21 Nov 2003 17:57:52 GMT, Jay Davis <> wrote:

    >Charles M. Elias wrote:
    >
    >> Make a VHDL model of the "rest of your circuit"--I'll call it
    >> device_b. Make a component of your FPGA device (device_a) and
    >> instantiate it in a testbench for device_b. Use the outputs of
    >> device_a (device_a is driven by the inputs you used to test it) as
    >> inputs to device_b. You "close the loop" by monitoring device_b's
    >> outputs and checking them for correctness either by inspection or by
    >> writing VHDL code to verify the outputs.

    >
    >Ah, I understand now. This would work if the "rest of my circuit" was
    >simple (just a few buttons and LEDs, as another poseter suggested), but
    >what I'm doing is interfacing a (256x128) LCD, and modeling an LCD in
    >VHDL isn't going to be practical.


    It might be. To model it exhaustively would be difficult.

    But to accept all the data fed to it (only 32kbits/frame?), or even only
    the top few rows to save simulation time, and verify (or log to disk) a
    small subset of that data (even an 8*8 cell in one corner) would be much
    easier, and could catch a lot of potential problems.

    - Brian
     
    Brian Drummond, Nov 22, 2003
    #7
  8. Jay Davis <> wrote:
    > I'm currently using Xilinx Webpack and modelsim to develop a project


    > project at home. I was wondering if there exists any sort of software
    > that would be able to drive the parallel port of a PC with the outputs
    > of a VHDL simulation? In other words, would it be possible to use a
    > simulation to drive some logic values onto the parallel port which I
    > could then pretend were the outputs of my FPGA chip (and then use those
    > outputs to test my VHDL code with the rest of my circuit)? I realize
    > that I would have some limitations on speed, but it ought to be
    > theoretically possible (or maybe not, that's why I'm asking!).


    Modelsim is able to to drive your parallelport via the FLI (foreign
    language interface). With the fli you can insert C-code in your
    simulation and drive the parport. It is not the easiest way and may
    took some time until you manage to get signals via the parport if your
    not familiar using the parport from C.
    I think our student apprentice took 3-4 weeks until he was able to use
    the parport with modelsim in both directions.

    bye Thomas
     
    Thomas Stanka, Nov 25, 2003
    #8
  9. Thomas Stanka wrote:
    >
    > Jay Davis <> wrote:
    > > I'm currently using Xilinx Webpack and modelsim to develop a project

    >
    > > project at home. I was wondering if there exists any sort of software
    > > that would be able to drive the parallel port of a PC with the outputs
    > > of a VHDL simulation? In other words, would it be possible to use a
    > > simulation to drive some logic values onto the parallel port which I
    > > could then pretend were the outputs of my FPGA chip (and then use those
    > > outputs to test my VHDL code with the rest of my circuit)? I realize
    > > that I would have some limitations on speed, but it ought to be
    > > theoretically possible (or maybe not, that's why I'm asking!).

    >
    > Modelsim is able to to drive your parallelport via the FLI (foreign
    > language interface). With the fli you can insert C-code in your
    > simulation and drive the parport. It is not the easiest way and may
    > took some time until you manage to get signals via the parport if your
    > not familiar using the parport from C.
    > I think our student apprentice took 3-4 weeks until he was able to use
    > the parport with modelsim in both directions.


    Unfortunately, the FLI is only available on the SE (super expensive :^)
    ) version of ModelSim.

    A possible brute-force method is to use ModelSim's Tcl scripting to
    execute an external (DOS) program each time you want to update the state
    of your parallel port. This is likely to be obscenely slow but it can be
    implemented with all versions of ModelSim. The Tcl commands you will
    need to read up on are "when" and "exec".
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Nov 25, 2003
    #9
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