receiving data

Discussion in 'VHDL' started by blackpadme, Oct 7, 2008.

  1. blackpadme

    blackpadme Guest

    Hi,

    I'm coding a data receiver which manage bits sent with period Tb. I
    need to do some operations with the actual input and the previous, and
    then, output the result.

    When i get the data from the channel, doing:

    get_data : process(clk, en)
    variable ...
    begin
    if en = '1' and rising_edge(clk) then
    temp_input := input;
    do things with input and the last value..

    output <= result;
    end process;

    I get a lag of Tb in the output. Is normal have this lag connecting
    sequential devices to other sequential devices receiving the data with
    a clock ?

    Thanks.
    blackpadme, Oct 7, 2008
    #1
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  2. blackpadme wrote:

    > ...
    > output <= result;
    > end process;
    >
    > I get a lag of Tb in the output. Is normal have this lag connecting
    > sequential devices to other sequential devices receiving the data with
    > a clock ?


    Yes. In your example,
    "result" is on the D side of the register, and
    "output" is on the Q side.

    -- Mike Treseler
    Mike Treseler, Oct 7, 2008
    #2
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