recommendation doing co-simulation between c/c++ with vhdl

Discussion in 'VHDL' started by Carson, Oct 5, 2005.

  1. Carson

    Carson Guest

    Hi,

    I would like to do co-simulation between c/c++ with vhdl code. In
    particular, i have a simulation chain coded in c/c++ (also providing
    test vectors) and would like to pass these test vectors to the vhdl
    module on the fly during testbench simulation.

    Since the simulation will run non-stop for long time, it would be
    preferable that the testbench won't need to read testvectors from a
    file. Is there any way to do that? I prefer hdl-simulation platform is
    modelsim.

    Thanks,

    Carson
    Carson, Oct 5, 2005
    #1
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