Record, Enumeration & std_logic_vector

J

Jan Kindt

Hi all,

I'm busy with some design where I use following types :

type e_DdrCmdType is (WrRq, RdRq);
type t_DdrCmd is record
CmdType : e_DdrCmdType;
RowNr : std_logic_vector(3 downto 0);
ColNr : std_logic_vector(10 downto 0);
BnkNr : std_logic;
end record;

I use the t_DdrCmd to transfer multiple signals from one entity to
another. So far so good. It results in clean, readable code.

Now I need to instantiate a precompiled fifo-core (Xilinx CoreGen)
which has std_logic_vector(16 downto 0) as input & output.

My problem is : how do I get the t_DdrCmd into the fifo ?

using ModelSim for simulation & XST for synthesis.

Thank you for all hints;..
 
M

Mike Treseler

Jan said:
I'm busy with some design where I use following types :
type e_DdrCmdType is (WrRq, RdRq);
type t_DdrCmd is record
CmdType : e_DdrCmdType;
RowNr : std_logic_vector(3 downto 0);
ColNr : std_logic_vector(10 downto 0);
BnkNr : std_logic;
end record;
I use the t_DdrCmd to transfer multiple signals from one entity to
another. So far so good. It results in clean, readable code.
Now I need to instantiate a precompiled fifo-core (Xilinx CoreGen)
which has std_logic_vector(16 downto 0) as input & output.
My problem is : how do I get the t_DdrCmd into the fifo ?

Just convert each field to a vector,then & the pieces together.
here's a sketch for your types:

entity record2std is
end record2std;

architecture sim of record2std
is

begin
what : process is
type e_DdrCmdType is (WrRq, RdRq);
type t_DdrCmd is
record
CmdType : e_DdrCmdType;
RowNr : std_logic_vector(3 downto 0);
ColNr : std_logic_vector(10 downto 0);
BnkNr : std_logic;
end record;

constant my_cmd : t_DdrCmd := (
CmdType => RdRq,
RowNr => "1001",
ColNr => "11110000111",
BnkNr => '0'
);
variable rd : std_ulogic;
variable fifo_word : std_logic_vector(16 downto 0);

begin
if my_cmd.CmdType = RdRq then
rd := '1';
else
rd := '0';
end if;

fifo_word := rd &
my_cmd.BnkNr &
my_cmd.RowNr &
my_cmd.ColNr;

wait;
end process what;

end sim; -- Mike Treseler
 
J

Jonathan Bromley

[that he wanted to convert between this structure...]
type e_DdrCmdType is (WrRq, RdRq);
type t_DdrCmd is record
CmdType : e_DdrCmdType;
RowNr : std_logic_vector(3 downto 0);
ColNr : std_logic_vector(10 downto 0);
BnkNr : std_logic;
end record;
[...and a 17-bit std_logic_vector.]

Just a few conversion functions, that's all.

The following could be coded more concisely using
aggregates and concatenations, but I rather like
the ability to use named subtypes and constants
to parameterise which bit goes where. (You haven't
told us that, so it needs to be flexible!!!)

Might be a good idea to put all this stuff in the
same package that defines the types, so it's all
gathered together in one place.

This is definitely OK with ModelSim; I haven't
checked whether XST is clever enough to synthesise it.
It shouldn't be a problem, but you never know...

----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use <whatever pkg defines your types>.all;

package DdrTypeMapper is

-- Subtype to reflect the FIFO i/o ports:
subtype slv_DdrCmd is std_logic_vector(16 downto 0);

-- Integer subtypes and constants that allow you to
-- parameterise which bits live where.
-- Constants for scalars, ranges for vectors.
constant slv_CmdType : natural := 16;
subtype slv_RowNr is natural range 15 downto 12;
subtype slv_ColNr is natural range 11 downto 1;
constant slv_BnkNr : natural := 0;

-- Convert between e_DdrCmdType and std_ulogic:
function to_sl(CmdType: e_DdrCmdType) return std_ulogic;
function to_e_DdrCmd(s: std_ulogic) return e_DdrCmdType;

-- Convert between slv_DdrCmd and t_DdrCmd:
function to_slv(cmd: t_DdrCmd) return slv_DdrCmd;
function to_t_DdrCmd(s: slv_DdrCmd) return t_DdrCmd;

end package DdrTypeMapper;

package body DdrTypeMapper is

-- Convert between e_DdrCmdType and std_ulogic:
function to_sl(CmdType: e_DdrCmdType) return std_ulogic is
begin
case CmdType is
when WrRq => return '0';
when RdRq => return '1';
end case;
end;
--
function to_e_DdrCmd(s: std_ulogic) return e_DdrCmdType is
begin
case s is
when '0'|'L' => return WrRq;
when '1'|'H' => return RdRq;
when others =>
report "metavalue in to_e_DdrCmd, returning WrRq"
severity WARNING;
return WrRq;
end case;
end;

-- Convert between slv_DdrCmd and t_DdrCmd:
function to_slv(cmd: t_DdrCmd) return slv_DdrCmd is
variable result: slv_DdrCmd;
begin
result(slv_CmdType) := to_sl(cmd.CmdType);
result(slv_RowNr) := cmd.RowNr;
result(slv_ColNr) := cmd.ColNr;
result(slv_BnkNr) := cmd.BnkNr;
return result;
end;

function to_t_DdrCmd(s: slv_DdrCmd) return t_DdrCmd is
variable result: t_DdrCmd;
begin
result.CmdType := to_e_DdrCmd(s(slv_CmdType));
result.RowNr := s(slv_RowNr);
result.ColNr := s(slv_ColNr);
result.BnkNr := s(slv_BnkNr);
return result;
end;

end package body DdrTypeMapper;
-----------------------------------------------------------

Hope this helps.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
J

Jan Kindt

Put all of this in my package.. Works perfectly !! except for the
report statement which I had to comment out to get modelsim to compile
it.. Dunno why, I've used this statement in other part of code & it
works perfect..

got an "error near 'report': expecting: END WHEN"

Thank you very much.é
 
J

Jonathan Bromley

Put all of this in my package.. Works perfectly !! except for the
report statement which I had to comment out to get modelsim to compile
it.. Dunno why, I've used this statement in other part of code & it
works perfect..

got an "error near 'report': expecting: END WHEN"

An old favourite: enable the compiler -93 option, because
-87 is the default (at least, until Modelsim 5.8 :-> ) and
the use of "report" without "assert" was added in VHDL'93.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
A

Allan Herriman

Put all of this in my package.. Works perfectly !! except for the
report statement which I had to comment out to get modelsim to compile
it.. Dunno why, I've used this statement in other part of code & it
works perfect..

got an "error near 'report': expecting: END WHEN"

Try the -93 switch on vcom to select the '93 language standard; report
doesn't exist in the '87 standard (which curiously is the default in
Modelsim).

Better still, edit your modelsim.ini file so that '93 is the default.

Regards,
Allan.
 

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