(refine question) vhdl and verilog simualtion

Discussion in 'VHDL' started by picnanard, Mar 14, 2009.

  1. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    Hi,

    Sorry for second thread, but i must be find solution for my job.

    I want launch simulation with architecture see attach file.
    I'm two component one in vhdl and other in verilog model inside SAME vhdl bench
    when can I launch this simulation?
    -Which tools? or
    -use netlist for the verilog model? or
    -when can i instantiate verilog model in vhdl bench?

    Modelsim doesn't support other hdl model.

    thank you,
    please help me,
     

    Attached Files:

    picnanard, Mar 14, 2009
    #1
    1. Advertising

  2. picnanard

    picnanard

    Joined:
    Mar 5, 2007
    Messages:
    19
    my sample mixed vhdl&verilog


    I try this mixed project in modelsim
    result
    # vsim work.bench
    # Loading std.standard
    # Loading ieee.std_logic_1164(body)
    # Loading std.textio(body)
    # Loading ieee.std_logic_textio(body)
    # Loading work.bench(t1)
    # version supports only a single HDL
    # ** Error: (vsim-3039) C:/Documents and Settings/hop/Bureau/VHDL&VERILOG/modelsim_small/bench.vhd(69): Instantiation of 'flipflop' failed.
    # Region: /bench
    # Error loading design

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_textio.all;
    -- use ieee.std_logic_unsigned.all;
    -- use ieee.std_logic_arith.all;

    entity bench is
    end bench;

    architecture T1 of bench is

    component flipflop
    port( q : in std_logic;
    ck : in std_logic;
    d : out std_logic);
    end component;

    constant XT_Tck : Time := 50 ns;

    -- Global signal


    signal Reset : std_logic;
    signal Clk ,Clk_n, q : std_logic;

    begin
    Reset <= '1', '0' after 100 ns ;

    Clk_n <= not Clk;

    Clock: process --20 Mhz---
    begin
    Clk<='1';
    Wait for XT_Tck/2;
    Clk<='0';
    Wait for XT_Tck/2;
    end process;

    bascule : flipflop --verilog modul
    port map (
    q => q,
    ck => clk,
    d => '1'
    );
    end T1;


    // bascule D sensible au front montant
    module flipflop( q, ck, d );
    input ck, d; output q;
    reg resu;
    always @ ( posedge ck ) resu = d;
    assign #1 q = resu;
    endmodule
     
    picnanard, Mar 14, 2009
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. marcoa.castellon@gmail.com

    Mixed VHDL and Verilog question

    marcoa.castellon@gmail.com, Dec 19, 2007, in forum: VHDL
    Replies:
    2
    Views:
    1,518
    Dwayne Dilbeck
    Dec 19, 2007
  2. Thomas Heller

    VHDL vs. verilog question

    Thomas Heller, Jul 28, 2010, in forum: VHDL
    Replies:
    19
    Views:
    1,438
    Marcus Harnisch
    Aug 4, 2010
  3. TLW

    Refine data displayed in datagrid

    TLW, Jan 23, 2007, in forum: ASP .Net Datagrid Control
    Replies:
    0
    Views:
    736
  4. _ugly

    warning: refine foo, what!?

    _ugly, Jul 3, 2005, in forum: Ruby
    Replies:
    4
    Views:
    112
    nobuyoshi nakada
    Jul 4, 2005
  5. Ethan Huo
    Replies:
    4
    Views:
    153
    Ethan Huo
    Apr 2, 2011
Loading...

Share This Page