regarding coding using signal assignment..........

Discussion in 'VHDL' started by ekavirsrikanth@gmail.com, Nov 3, 2006.

  1. Guest

    i have a doubt regarding the coding style in vhdl
    ........................


    if ( reset = '1' ) then


    data_temp <= 0;


    elsif (clock'event and clock = '1') then


    data <= data_temp;
    data_out <= data_temp and not data;


    end if;
    end if;


    1. when i am giving clock data temp data is loaded into data at

    present clock cycle or at next clock cycle.


    2. when i am taking data_out output as given above it is
    getting data_out at next clock cycle not at the present clock cycle
    where data_temp is high and data is low. why this is happening


    i need to get the data_out (high for one clock cycle at the
    instant data_temp is high not at the next clock cycle .)


    is this problem will be solved during synthesis since i am
    facing the problem during simulation but does it behave the same way
    during synthesis also. since it is a signal assignment signal " <= " a

    minimum of delta delay will be there but will it take the entire clock
    cycle delay.........


    regards
    kil
    , Nov 3, 2006
    #1
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  2. schrieb:

    > if ( reset = '1' ) then
    >
    >
    > data_temp <= 0;
    >
    >
    > elsif (clock'event and clock = '1') then
    >
    >
    > data <= data_temp;
    > data_out <= data_temp and not data;
    >
    >
    > end if;
    > end if;
    >
    >
    > 1. when i am giving clock data temp data is loaded into data at
    >
    > present clock cycle or at next clock cycle.


    Simulate it! ;-)

    All signals are updated after a delta delay. This means for "data", that
    the new value ("data_temp") will be assigned to "data" in the next delta
    delay. A delta delay is only a step of the simulator in reality it is
    zero time.



    > 2. when i am taking data_out output as given above it is
    > getting data_out at next clock cycle not at the present clock cycle
    > where data_temp is high and data is low. why this is happening


    Again the delta delay is the reason for this: The new values of "data"
    and "data_out" will be written in the next delta delay. At the moment
    the simulator read the _old_ value of these signals.

    This has an expression in reality: bot "data" and "data_out" are
    flipflops. If you read the value of data_out at the same time when
    "data" gets a new value, then you see the old value at the output of the
    "data" flipflop. The signal has to propagate through the flipflop, which
    takes some time.


    > i need to get the data_out (high for one clock cycle at the
    > instant data_temp is high not at the next clock cycle .)


    I am not shure if I understand you right, but I guess that

    data_out <= data_temp;

    would lead to the solution you look for. Why do you need "data"?



    > is this problem will be solved during synthesis since i am
    > facing the problem during simulation but does it behave the same way
    > during synthesis also. since it is a signal assignment signal " <= " a


    You described 2 flipflops in a chain. Therefore you see the same
    behavior after synthesis.


    > minimum of delta delay will be there but will it take the entire clock
    > cycle delay.........


    A delta delay has zero time length.
    A VHDL simulator works hardly as follows:
    * If there is a an event of a signal, then evaluate, what will happen.
    In our case let the event be the rising_edge(clock).
    * During evaluation the new values of all signals will be computed. The
    new values will be not stored at the signals immediately, because the
    simulator does not know, which signal has to be updated before an
    other. Therefore the new values are scheduled for being stored later -
    in the next simulator step after one delta cycle.
    * After all values of all signals have been computed, evaulation is done
    and the simulator advances to the next step - a delta delay later.
    Then the simulator assigns the previously computed values to the
    signals.


    Variables get their values immediately - not after a delta delay. Thats
    one difference to signals.

    Ralf
    Ralf Hildebrandt, Nov 3, 2006
    #2
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  3. krushi

    Joined:
    May 17, 2006
    Messages:
    1
    :shake: Thanks Ralf,

    i need to generate the data_out for a clock cycle and then it will be disabled so i to that i have generated the data signal and doing the not operation so that i will get the data_out for one clock cycle thats what my reqirment is but insted i am getting the data_out at the clock event data is high (what i need is data_out to be high at present clock event where data_temp is high and data is low).

    thanks for the reply............

    regards

    krushi
    krushi, Nov 6, 2006
    #3
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