Regarding to the DUT configuration in testbench

Discussion in 'VHDL' started by JSreeniv, Jul 29, 2011.

  1. JSreeniv

    JSreeniv Guest

    Hi,

    I was exploring the DUT connectivity with my testbench(TB). What i am
    doing: With my encrypted DUT i wrote a TB (for reception) MIL 1553 FE
    by configuring the register to the mode as RT and start sending the
    command and number of data on 1553_rx lines (where the command and
    data are Valid) w.r.t the standard and after some response time the
    transmitter will send a status word followed by data word on 1553_tx
    lines.
    The actual query is that can i configure one DUT as BC mode and again
    same DUT as RT mode (Here we can change DUT names while configuring in
    ModelSim) so that my TB can handle the communication between BC and RT
    mode.

    Since i have only RT terminal register set i can access whatever i
    want, but i don't have register set for BC but mode setting facility
    is available for the register.

    Could anyone suggest me whether this is possible or not and some more
    analysis.

    Thanks
    Nivas.
    JSreeniv, Jul 29, 2011
    #1
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  2. JSreeniv

    sri.cvcblr

    Joined:
    Aug 4, 2011
    Messages:
    2
    Location:
    Bangalore India
    I am not sure I understood your requirement fully. But in short - you want your TB to be talking to one set of "interface" for a while and within the same simulation, talk to a different set. Ideally this is what SystemVerilog's virtual interface can provide you. In case you want to hand-code it, you will need to do "pin-muxing" yourself. Not hard, but requires clear TB architecture.

    Regards
    Srini
    www.cvcblr.com/blog
    sri.cvcblr, Aug 4, 2011
    #2
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