Register File In VHDL

[midin]

Hello, I'm competing this problem - I have to write an architecture for a register file (while the entity is given below), but I totally don't know how to do this.. If you are able to post some helpy post, I'd be very glad, thanks.


-- rf.vhd : Register file

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity rf is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2
);
port (
RESET : in std_logic; -- reset
CLK : in std_logic; -- clock

-- Write port
WR_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
WR_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
WR_WE : in std_logic;

-- Read port A
RDA_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
RDA_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);

-- Read port B
RDB_ADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
RDB_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0)

);
end rf;


-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of rf is

-- SIGNALS

begin

-- IMPLEMENTATION

end behavioral;

 

[midin]

Ok, I've probably managed to create the signal part, but what about the implementation, does anybody know?

Signal part (must be done through generic parameters ADDR_WIDTH, DATA_WIDTH), creates an array of registers:

constant ARR_SIZE : integer := 2^ADDR_WIDTH;
type array_type is array(0 to ARR_SIZE-1) of std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
signal reg : array_type;

 

[joris]

I think reading a bit on sequential logic in VHDL should help...

 

[midin]

Yes, I think so, there would be no problem if it has not to be done with those generic parameters.. Maybe this code? I'm not really able to simulate this because of my PC health conditions..

reg_sim: process (RESET, CLK)
begin

if (RESET = '1') then
reg(WR_ADDR) <= (others => '0');
elsif (CLK 'EVENT) and (CLK= '1') then
if (WR_WE = '1') then
reg(WR_ADDR) <= WR_DATA;
end if;
end if;

end process;

 

[joris]

If you also add the reads in the process it renders a register file.

You may want to declare the register array as a variable inside the process. That way,
if WR_ADDR = RDA_ADDR or WR_ADDR = RDB_ADDR, you will get the newly written value returned.
(if this case can happen and it is a wanted property, otherwise keep it as a signal)

Also in the RESET part, initialise all registers, not just the one indicated with WR_ADDR (which most likely isn't a valid value anyway at that point):
reg <= (others => (others => '0'));

 

[midin]

Thank you so much, I'm pretty sure this will help.

 

[m.oaklander]

Hello. I searched the internet for a solution to my problem and I found that you have found a solution that he most resembles. True, my problem is slightly different, but the results are based on the same basis. Can you tell me how you finally solved your code (Registry File In VHDL)? It would be a help to me, although I had to redo your code in my needs. Thanks for the reply. If you're willing to write to m.oaklander111 @ gmail.com.
Sincerely, Mike. :ciao: